Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)最新文献_第3页

HiPCrypto: a high-performance VLSI cryptographic chip HiPCrypto:高性能VLSI加密芯片

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722785

S. Salomão, V. Alves, E. Filho

引用次数: 23

A customizable DSP for DMT-based ADSL modem 基于dmt的ADSL调制解调器的可定制DSP

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.723033

L. Kiss, E. Hanssens, K. Adriaensen, M. Huysmans, C. Gendarme, E. Van Beylen, H. Van De Weghe

引用次数: 4

Dsm Interconnect Modeling And Analysis For Performance And Reliability 基于性能和可靠性的Dsm互连建模与分析

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.723091

A. Kahng, S. Muddut

引用次数: 0

A proven embedded DRAM compiler for deep submicron logic processes and system-on-a-chip ASIC designs 经过验证的嵌入式DRAM编译器，用于深亚微米逻辑处理和片上系统ASIC设计

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722901

T. Tsang, B. Rodriguez, G. Haag, H. Crafts

引用次数: 0

Development of Mitsubishi precision scale controller 三菱精密秤控制器的研制

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722789

T. Matsukawa, M. Mizoguchi, K. Takeuchi

引用次数: 1

Optimum repeater insertion based on a CMOS delay model for on-chip RLC interconnect 基于CMOS延迟模型的片上RLC互连中继器最佳插入

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.723040

Yehea Ismail, Eby G. Friedman

{"title":"Optimum repeater insertion based on a CMOS delay model for on-chip RLC interconnect","authors":"Yehea Ismail, Eby G. Friedman","doi":"10.1109/ASIC.1998.723040","DOIUrl":"https://doi.org/10.1109/ASIC.1998.723040","url":null,"abstract":"A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 7% of SPICE simulations for a wide range of RLC loads. This expression is based on the alpha power law for deep submicrometer technologies. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a distributed RC line can be over 30% for present on-chip interconnect. It is also shown that the traditional quadratic dependence of the propagation delay on the length of the interconnect for RC lines approaches a linear dependence as inductance effects increase, which is expected to have a profound effect on traditional design methodologies. The closed form CMOS delay model is applied to the problem of repeater insertion in RLC interconnect. Closed form solutions are presented for inserting repeaters into RLC lines that are highly accurate with respect to numerical solutions. It is shown that large errors in the repeater design process are encountered if inductance is neglected. Errors up to 30% can occur if repeaters are inserted without considering the effects of inductance. The error between the RC and RLC models increases as the gate parasitic impedances decrease. Thus, the importance of inductance in high performance VLSI design methodologies will increase as technologies scale.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131966884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 46

Novel Devices And Circuits 新型器件和电路

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722820

J. Chickanosky, R. Frye

引用次数: 0

Asic Cad Applications And Algorithms Asic Cad应用与算法

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722890

R. Auletta, Mely Chen Chi

{"title":"Asic Cad Applications And Algorithms","authors":"R. Auletta, Mely Chen Chi","doi":"10.1109/ASIC.1998.722890","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722890","url":null,"abstract":"Computer-aided design is central to ASIC design, supporting the design process from specification to implementation. The papers presented in this year’s CAD session reflect the broad importance of CAD in the ASIC design process, with papers addressing both the application of ASIC EDA tools, complete tool suites, and the algorithms they use. The session opens with a case study by Alcatel and Toshiba on CAD design methods for million gate systems. The session then addresses the application of CAD tools for the design of a Fast Discrete Cosine Transform and an embedded DRAM compiler for systems on a chip. Automatic layout synthesis and power estimation are covered in the next two papers. The first describes automatic layout of dynamic CMOS circuits and the second describes architectural estimation of power dissipation in processor control units. Finally the session closes with the presentation of papers on CAD algorithms, including a paper on incremental rerouting of mapped FPGA circuits and two papers on VLSI circuit partitioning. The first applies TABU intelligent problem solving to bipafl itioning, while the second reports on improved wirelengths by relaxing the traditional bisection constraint.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128683009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Relaxed partitioning balance constraints in top-down placement 在自上而下的布局中放松分区平衡约束

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722911

A. Caldwell, A. Kahng, I. Markov

引用次数: 9

Design and test of a CMOS low-power mixed-analog/digital ASIC for radiation detector readout front ends 用于辐射探测器读出前端的CMOS低功耗模拟/数字混合ASIC的设计与测试

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722809

L. Hebrand, J. Blonde, C. Colledani, G. Clauss

引用次数: 6