{"title":"Dsm Interconnect Modeling And Analysis For Performance And Reliability","authors":"A. Kahng, S. Muddut","doi":"10.1109/ASIC.1998.723091","DOIUrl":null,"url":null,"abstract":"DSM interconnects have a dominant impact on the achievable performance of integrated circuits. A broad spectrum of issues must be dealt with by design tools and methodologies to achieve successful outcomes. This tutorial develops the fundamentals of DSM interconnect modeling and analysis, starting with the underlying process technology and design methodology contexts, and continuing with interconnect performance and reliability analyses, frontend interconnect metrics and models, and modeling for interconnect synthesis and optimization. The tutorial’s intended audience consists of ASIC designers, design tool users, and CAD developers. The material will be presented in a form (slides, pseudocode fragments, reference lists) that attendees can take away and immediately use.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1998.723091","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
DSM interconnects have a dominant impact on the achievable performance of integrated circuits. A broad spectrum of issues must be dealt with by design tools and methodologies to achieve successful outcomes. This tutorial develops the fundamentals of DSM interconnect modeling and analysis, starting with the underlying process technology and design methodology contexts, and continuing with interconnect performance and reliability analyses, frontend interconnect metrics and models, and modeling for interconnect synthesis and optimization. The tutorial’s intended audience consists of ASIC designers, design tool users, and CAD developers. The material will be presented in a form (slides, pseudocode fragments, reference lists) that attendees can take away and immediately use.