A proven embedded DRAM compiler for deep submicron logic processes and system-on-a-chip ASIC designs

This paper covers the motivations for and the advantages of using an embedded DRAM compiler technology within a standard deep submicron logic process for System-on-a-Chip (SoC). We also discuss the bit cell design and the memory architecture, as well as the automation software and methodology used in the construction of the DRAM compiler. Silicon results from the test chips are favorable. This approach makes economical and time-to-market sense, therefore it can be a viable high-performance and area-efficient option in the embedded DRAM technology.