CMOS标准单元中的440 MHz 16位计数器

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI:10.1109/ASIC.1998.722966

B. Hoppe, C. Kroh, H. Meuth, M. Stohr

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引用次数: 11

摘要

我们提出了一种高速计数器架构，其工作在0.7 /spl mu/m CMOS标准单元中，测量时钟速率为440 MHz。基本架构提供了以下关键特征:(a)速度性能基本上只受单个触发器延迟的限制;(b)计数器状态在一个时钟周期内稳定到实际状态。

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A 440 MHz 16 bit counter in CMOS standard cells

We present a high speed counter architecture, which operates in 0.7 /spl mu/m CMOS standard cells at a measured clock rate of 440 MHz. The basic architecture provides the following key features: (a) the speed performance is essentially limited only by the delay of a single flip-flop; (b) the counter state stabilizes to the actual state within a single clock cycle.

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来源期刊

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)

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