Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)最新文献_第3页

Utilization of quartile analysis in process control 四分位分析在过程控制中的应用

Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130) Pub Date : 2000-09-26 DOI: 10.1109/ISSM.2000.993708

A. El-Sayed, C. Montgomery, S. Jenkins

{"title":"Utilization of quartile analysis in process control","authors":"A. El-Sayed, C. Montgomery, S. Jenkins","doi":"10.1109/ISSM.2000.993708","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993708","url":null,"abstract":"This paper addresses the utilization of quartile analysis in correlating inline measurements to end of line yield and electrical parametrics outliers (tail of population) over a large sample of lots to reduce the signal to noise ratio. In this paper we will discuss four case studies for a .25 /spl mu/m CMOS technology in a high volume-manufacturing environment where quartile analysis was used and proved successful. Case study A is addressing a .5% process yield loss due to high via resistance. Quartile (QTR) analysis of via resistance vs. key in-line processes indicated sensitivities to inter-metal-dielectric (IMD) thickness and via size. Case study B is utilizing QTR analysis to determine optimum contact etch time to overcome marginality to poly-metal-dielectric (PMD) thickness without compromising device diode leakage. Case Study C correlated a functional yield loss at the edge of the wafer to high TiN target life. Case Study D correlated titanium (Ti) kit life to high via Kelvin. In these case studies, quartile analysis was effectively used to analyze large sample of lots, evaluate current process control limits, identify any process marginalities, and drive corrective actions.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125035987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Potential propagation model-based failure analysis support tool for MOS LSIs 基于潜在传播模型的MOS lsi失效分析支持工具

Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130) Pub Date : 2000-09-26 DOI: 10.1109/ISSM.2000.993661

M. Kodama, H. Kakinuma, J. Kumagai, H. Niina, J. Kiji

引用次数: 0

Enhanced quality of tunnel oxide by in-situ screen oxide for embedded flash memory application 利用原位氧化屏提高隧道氧化物的质量，用于嵌入式快闪存储器

Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130) Pub Date : 2000-09-26 DOI: 10.1109/ISSM.2000.993705

T. Nakamura, M. Ichii

{"title":"Enhanced quality of tunnel oxide by in-situ screen oxide for embedded flash memory application","authors":"T. Nakamura, M. Ichii","doi":"10.1109/ISSM.2000.993705","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993705","url":null,"abstract":"We have developed flash-memory-integrated VLSI logic chips. The base technology is logic process and logic design system is fully utilized for this chip design. In the flash memory, tunnel oxide film plays very important roles for data retention, write, and erase operations. Especially data retention is one of the most important parameters. Flash memory data is stored as electrons in the conductor isolated by tunnel oxide. Therefore, data retention performance is mainly dominated by electron leakage property of the tunnel oxide film. In this paper, tunnel oxide electron leakage dependency on the following two process conditions is described One is the wafer position in the tunnel oxide growth furnace tube. Wafers loaded at the bottom of the furnace boat showed lower electron leakage. The other is in-situ screen oxide formation at tunnel oxide formation. In-situ oxidation just prior to the tunnel oxide growth forms 2-3 nm-screen oxide. This screen oxide reduces electron leakage current through tunnel oxide. Tunnel oxide surface roughness was measured by Atomic Force Microscope (AFM) to evaluate electron leakage through tunnel oxide. In-situ screened tunnel oxide showed smoother surface than that of non-screened tunnel oxide. Data retention performance is improved as the tunnel oxide surface get smoother.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128653208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Cost and initial performance observations of CMP vs. spin-etch processing for removal of copper metalization from patterned low-k materials CMP与自旋蚀刻工艺在低k材料中去除铜金属化的成本和初始性能观察

Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130) Pub Date : 2000-09-26 DOI: 10.1109/ISSM.2000.993639

P. Lysaght, W. Mlynko, P. Lefèvre, I. Ybarra

引用次数: 1

Defect mode classification in logic LSI manufacturing process using I/sub DDQ/ 基于I/sub / DDQ/的逻辑LSI制造过程缺陷模式分类

Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130) Pub Date : 2000-09-26 DOI: 10.1109/ISSM.2000.993659

M. Sanada, K. Uehira, E. Fuse

引用次数: 1

Approach for environmental standard with etch tools 蚀刻工具环境标准的方法

Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130) Pub Date : 2000-09-26 DOI: 10.1109/ISSM.2000.993675

K. Fukasawa, T. Kitoku, A. Kobayashi, Y. Hirayama, M. Saito, K. Nagaseki

引用次数: 1

Petri net simulation of manufacturing systems considering multiple machines, operators, and maintenance for a product-mix Petri网模拟的制造系统考虑多机器，操作员和维护的产品组合

Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130) Pub Date : 2000-09-26 DOI: 10.1109/ISSM.2000.993682

S. Arima, K. Saito

引用次数: 1

Intelligent yield prediction models for high-speed microprocessors 高速微处理器的智能良率预测模型

Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130) Pub Date : 2000-09-26 DOI: 10.1109/ISSM.2000.993644

Tae Seon Kim, Se-Hwan Ahn, Y. Jang, Jeong In Lee, Kil Jae Lee, B. Kim, Chang Hyun Cho

引用次数: 1

Aluminum grain interaction with metal etch induced by TiN film thickness TiN膜厚度诱导铝晶粒与金属蚀刻的相互作用

Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130) Pub Date : 2000-09-26 DOI: 10.1109/ISSM.2000.993706

J. Campbell, A. Griffin, J. Manzay, A. Oliva

引用次数: 1

Implementation requirements for edge exclusion area reduction for maximized output of chips from a 200 mm wafer 减小边缘排除面积的实施要求，以使200毫米晶圆的芯片输出最大化

Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130) Pub Date : 2000-09-26 DOI: 10.1109/ISSM.2000.993625

S. Kawashima, S. Nukii

{"title":"Implementation requirements for edge exclusion area reduction for maximized output of chips from a 200 mm wafer","authors":"S. Kawashima, S. Nukii","doi":"10.1109/ISSM.2000.993625","DOIUrl":"https://doi.org/10.1109/ISSM.2000.993625","url":null,"abstract":"Productivity improvement is one of the most important factors to reduce manufacturing costs for all semiconductor manufacturing companies and refers to how many functionally good chips can be manufactured from one wafer. Edge exclusion area reduction is one of the most effective methods for productivity improvement as well as yield improvement actions, and a gain of the number of valid chips inside the edge exclusion area does not depend on the chip size. We discuss the implementation requirements of edge exclusion area reduction by understanding quality level, thickness uniformity, and particle deposition of processing tools, and the essential requirements for edge exclusion area reduction are reduce yield variations within the wafer, understand thickness non-uniformity for processing tools and minimize areas where yield is affected, avoid clamps for wafer handling mechanisms, and use die-to-die comparisons to check for size uniformity among wafer-edge chips Therefore the conclusion is that a 5 mm edge exclusion can be reduced to a 3 mm edge exclusion.","PeriodicalId":104122,"journal":{"name":"Proceedings of ISSM2000. Ninth International Symposium on Semiconductor Manufacturing (IEEE Cat. No.00CH37130)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134515940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1