Cost and initial performance observations of CMP vs. spin-etch processing for removal of copper metalization from patterned low-k materials

Abstract

While copper is rapidly replacing aluminum as the main on-chip conductor, new dielectric materials are being investigated as potential replacements for silicon dioxide (SiO/sub 2/, k=3.9) to reduce the capacitance component of RC interconnect delays. We identify integration challenges and addresses potential solutions pertaining to the manufacture of copper/low-k dual damascene structures at International SEMATECH (ISMT). Results of initial investigations of the feasibility of wet spin-etch processing (SEP) as an alternative to chemical-mechanical polishing (CMP) for the removal of electroplated copper overburden from a film stack that includes soft, compressible low-k dielectric material are presented. Chemical consumption per wafer for the two processes is also presented.