Utilization of quartile analysis in process control

Abstract

This paper addresses the utilization of quartile analysis in correlating inline measurements to end of line yield and electrical parametrics outliers (tail of population) over a large sample of lots to reduce the signal to noise ratio. In this paper we will discuss four case studies for a .25 /spl mu/m CMOS technology in a high volume-manufacturing environment where quartile analysis was used and proved successful. Case study A is addressing a .5% process yield loss due to high via resistance. Quartile (QTR) analysis of via resistance vs. key in-line processes indicated sensitivities to inter-metal-dielectric (IMD) thickness and via size. Case study B is utilizing QTR analysis to determine optimum contact etch time to overcome marginality to poly-metal-dielectric (PMD) thickness without compromising device diode leakage. Case Study C correlated a functional yield loss at the edge of the wafer to high TiN target life. Case Study D correlated titanium (Ti) kit life to high via Kelvin. In these case studies, quartile analysis was effectively used to analyze large sample of lots, evaluate current process control limits, identify any process marginalities, and drive corrective actions.