Potential propagation model-based failure analysis support tool for MOS LSIs

Abstract

This paper presents an efficient failure analysis method using a MOS LSI failure analysis system, named Failure Analysis Support Tool (FAST). When LSI design data, test patterns and test conditions are input into FAST, it calculates the potential in integrated circuits based on our proposing Potential Propagation model, and outputs the result as a timing diagram. The location of electrical faults can then be identified using the timing diagram FAST even allows engineers without detailed knowledge of the design to analyze failures in the device swiftly and accurately. This method is useful for logic LSIs and the peripheral circuits of memory LSIs, where faults are often difficult to locate.