Implementation requirements for edge exclusion area reduction for maximized output of chips from a 200 mm wafer

Abstract

Productivity improvement is one of the most important factors to reduce manufacturing costs for all semiconductor manufacturing companies and refers to how many functionally good chips can be manufactured from one wafer. Edge exclusion area reduction is one of the most effective methods for productivity improvement as well as yield improvement actions, and a gain of the number of valid chips inside the edge exclusion area does not depend on the chip size. We discuss the implementation requirements of edge exclusion area reduction by understanding quality level, thickness uniformity, and particle deposition of processing tools, and the essential requirements for edge exclusion area reduction are reduce yield variations within the wafer, understand thickness non-uniformity for processing tools and minimize areas where yield is affected, avoid clamps for wafer handling mechanisms, and use die-to-die comparisons to check for size uniformity among wafer-edge chips Therefore the conclusion is that a 5 mm edge exclusion can be reduced to a 3 mm edge exclusion.