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Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)最新文献

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A fast-lock mixed-mode DLL using a 2-b SAR algorithm 使用2-b SAR算法的快速锁定混合模式DLL
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929827
G. Dehng, Jyh-Woei Lin, Shen-Iuan Liu
{"title":"A fast-lock mixed-mode DLL using a 2-b SAR algorithm","authors":"G. Dehng, Jyh-Woei Lin, Shen-Iuan Liu","doi":"10.1109/CICC.2001.929827","DOIUrl":"https://doi.org/10.1109/CICC.2001.929827","url":null,"abstract":"In this paper, a fast-lock mixed-mode DLL (MMDLL) is presented. The digital part of the MMDLL utilizes a 2-b SAR algorithm to achieve short lock time compared to the conventional RDLL, CDLL and SARDLL, while the analog part helps to reduce the static phase error and improve the output clock jitter. The measured output clock rms, peak-to-peak jitter and static phase error are 6.6 ps, 47 ps and 12.4 ps, respectively at 100 MHz and the power consumption is 15.8 mW in the locked state at 2.7 V supply voltage. The maximum lock time is 13.5 clock cycles when the static phase error is within 1 LSB (156 ps).","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123418677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
Silicon-germanium BiCMOS technology and a CAD environment for 2-40 GHz VLSI mixed-signal ICs 2- 40ghz VLSI混合信号集成电路的硅锗BiCMOS技术和CAD环境
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929842
S. Subbanna, L. Larson, G. Freeman, D. Ahlgren, K. Stein, C. Dickey, J. Mecke, A. Rincon, P. Bacon, R. Groves, M. Soyuer, D. Harame, J. Dunn, D. Rowe, W. Chon, D. Herman, B. Meyerson
{"title":"Silicon-germanium BiCMOS technology and a CAD environment for 2-40 GHz VLSI mixed-signal ICs","authors":"S. Subbanna, L. Larson, G. Freeman, D. Ahlgren, K. Stein, C. Dickey, J. Mecke, A. Rincon, P. Bacon, R. Groves, M. Soyuer, D. Harame, J. Dunn, D. Rowe, W. Chon, D. Herman, B. Meyerson","doi":"10.1109/CICC.2001.929842","DOIUrl":"https://doi.org/10.1109/CICC.2001.929842","url":null,"abstract":"SiGe BiCMOS technology provides a stable, ultra-high performance, semiconductor technology capable of supporting large mixed-signal VLSI circuit designs for a variety of emerging communications applications. This technology has been wedded to a CAD system that supports a variety of high-performance circuit designs, mixed-signal circuit block re-use, and the ability to accurately predict circuit performance at the highest frequencies. This paper will summarize the progress this technology has made in recent years in moving from the research laboratory into a production environment.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123750264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A differential bipolar quasi-passive cyclic digital-to-analog converter with 4.416 MSps conversion rate and -77 dB THD 差分双极准无源循环数模转换器，转换速率为4.416 MSps, THD为-77 dB
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929747
M. Moussavi, R. Mason, C. Plett
{"title":"A differential bipolar quasi-passive cyclic digital-to-analog converter with 4.416 MSps conversion rate and -77 dB THD","authors":"M. Moussavi, R. Mason, C. Plett","doi":"10.1109/CICC.2001.929747","DOIUrl":"https://doi.org/10.1109/CICC.2001.929747","url":null,"abstract":"Cyclic Digital-to-Analog Converters (DACs) can provide low power alternatives to current steering DACs for medium conversion rates. A cyclic DAC capable of achieving lite-rate DSL performance for downstream is presented in this paper. With the help of a differential bipolar architecture, the DAC delivers close to 12 bits of linearity at 4.416 MS/s conversion rate. The cyclic D/A converter, implemented in a 0.35-/spl mu/m double-poly CMOS technology, dissipates only 10 mW.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121296968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Circuits for on-chip sub-nanosecond signal capture and characterization 片上亚纳秒级信号捕获和表征电路
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929766
N. Abaskharoun, G. Roberts
{"title":"Circuits for on-chip sub-nanosecond signal capture and characterization","authors":"N. Abaskharoun, G. Roberts","doi":"10.1109/CICC.2001.929766","DOIUrl":"https://doi.org/10.1109/CICC.2001.929766","url":null,"abstract":"Two circuits for performing on-chip subnanosecond signal measurements are presented. The first is an on-chip digitizer capable of capturing high-bandwidth arbitrary periodic signals, The second is a specialized jitter measurement structure based on a Time-to-Digital Converter (TDC). Both circuits were successfully implemented in a 0.35 /spl mu/m CMOS process. The digitizer is capable of capturing signals at an effective sampling rate of 1.6 GWz, while the jitter measurement device can measure jitter with an 18 ps resolution.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"354 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126687809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
An efficient method of applying hot-carrier reliability simulation to logic design 一种将热载流子可靠性仿真应用于逻辑设计的有效方法
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929770
H. Sato, Mariko Ohtsuka, K. Yanagisawa, P. M. Lee
{"title":"An efficient method of applying hot-carrier reliability simulation to logic design","authors":"H. Sato, Mariko Ohtsuka, K. Yanagisawa, P. M. Lee","doi":"10.1109/CICC.2001.929770","DOIUrl":"https://doi.org/10.1109/CICC.2001.929770","url":null,"abstract":"This paper presents an efficient application of hot carrier reliability simulation to 0.18 /spl mu/m and 0.14 /spl mu/m gate length logic products. Using analysis of simple primitive inverter cells, a design rule was developed in restricting signal rise time, and delay libraries of actual products which were screened to check whether the rise time restrictions were met. At 200 MHz, maximum rise time (0-100%) triseMAX was 0.8 ns (17% of duty) under /spl Delta/td/td=5%. For a 800,000 net product, only 25 simulations were done (each less than one minute CPU time) for the internal devices with screening done for this logic process. 30 nets were caught, but judged reliable due to their reduced duty.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127006999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Impact of within-die parameter fluctuations on future maximum clock frequency distributions 模内参数波动对未来最大时钟频率分布的影响
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929761
K. Bowman, J. Meindl
{"title":"Impact of within-die parameter fluctuations on future maximum clock frequency distributions","authors":"K. Bowman, J. Meindl","doi":"10.1109/CICC.2001.929761","DOIUrl":"https://doi.org/10.1109/CICC.2001.929761","url":null,"abstract":"The impact of parameter fluctuations on future circuit performance is evaluated by employing rigorously derived device and circuit models to calculate the critical path delay distributions resulting from die-to-die and within-die fluctuations. Utilizing these distributions with a recently derived FMAX distribution model validated by measured data, the effect of within-die fluctuations on the FMAX mean is forecast for the 180, 130, 100, 70 and 50 nm technology generations. Systematic within-die fluctuations impose the largest performance degradation resulting from parameter fluctuations. Assuming a 3/spl sigma/ channel length deviation of 20%, projections for the 50 nm technology generation indicate that essentially a generation of performance gain can be lost due to systematic within-die fluctuations. This analysis should encourage efforts toward tightening within-die process controls and developing circuit design methodologies that suppress the impact of within-die parameter fluctuations on circuit performance.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"370 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115904564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
Interface circuit for metal-oxide gas sensor 金属氧化物气体传感器接口电路
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929735
Pierre-François Ruedi, P. Heim, A. Mortara, E. Franzi, H. Oguey, X. Arreguit
{"title":"Interface circuit for metal-oxide gas sensor","authors":"Pierre-François Ruedi, P. Heim, A. Mortara, E. Franzi, H. Oguey, X. Arreguit","doi":"10.1109/CICC.2001.929735","DOIUrl":"https://doi.org/10.1109/CICC.2001.929735","url":null,"abstract":"This paper describes a sensor interface for metal-oxide chemical gas sensor for pollution detection. The function of the ASIC is to control the sensor working temperature by applying a programmable voltage with 10 bit resolution, to measure the resistance of the sensitive elements ranging from 5 k/spl Omega/ to 100 M/spl Omega/, measure the ambient temperature with an external NTC thermistor and offer a fully digital user interface. It gives the possibility to make low power and low cost high performance gas sensing microsystems for consumer application.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115747885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A 1.0 V GHz range 0.13 /spl mu/m CMOS frequency synthesizer 1.0 V GHz范围0.13 /spl mu/m CMOS频率合成器
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929792
Lizhong Sun, D. Nelson
{"title":"A 1.0 V GHz range 0.13 /spl mu/m CMOS frequency synthesizer","authors":"Lizhong Sun, D. Nelson","doi":"10.1109/CICC.2001.929792","DOIUrl":"https://doi.org/10.1109/CICC.2001.929792","url":null,"abstract":"A 0.13 /spl mu/m CMOS user programmable PLL frequency synthesizer is designed to operate at low voltage (1.0-1.8 V) and cover a wide range of operating frequencies for multiple applications. This design incorporates low voltage circuits and a digital auto-trimming scheme which calibrates the center frequency of the VCO and limits the VCO gain variation for stability and reduced jitter over all process and temperature conditions. The maximum frequency is 1.25 GHz and 2.85 GHz at 1.0 V and 1.8 V supply voltages, respectively. Period jitter at 1 GHz output is 4.9 ps (r.m.s.) and 45.8 ps (p-p) with a power consumption of 3.9 mW for 1.0 V supply.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128421527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Single-chip 10.7 gb/s FEC codec LSI using time-multiplexed RS decoder 单片10.7 gb/s FEC编解码LSI采用时复用RS解码器
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929778
K. Seki, Kousuke Mikami, M. Baba, N. Shinohara, S. Suzuki, H. Tezuka, S. Uchino, N. Okada, Y. Kakinuma, A. Katayama
{"title":"Single-chip 10.7 gb/s FEC codec LSI using time-multiplexed RS decoder","authors":"K. Seki, Kousuke Mikami, M. Baba, N. Shinohara, S. Suzuki, H. Tezuka, S. Uchino, N. Okada, Y. Kakinuma, A. Katayama","doi":"10.1109/CICC.2001.929778","DOIUrl":"https://doi.org/10.1109/CICC.2001.929778","url":null,"abstract":"This paper describes a 10.7 Gb/s throughput FEC (Forward Error Correction) codec LSI for optical transmission systems. In order to reduce the power consumption and logic size, the FEC codec uses a time-multiplexed Reed-Solomon (RS) decoder, which is shared among 4 RS codewords and processes 5 parallel digits. The time-multiplexed RS decoder requires only 58% of the gates and 75% of the power consumption of the conventional decoder. As a result, the codec achieves a low power consumption of only 3.31 W and a low gate count of only 1.1 Mgates using 0.18 /spl mu/m CMOS technology.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130625614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Circuits and technologies for highly integrated optical networking ICs at 10 Gb/s to 40 Gb/s 10gb /s ~ 40gb /s高集成光网络ic电路与技术
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929795
S. Voinigescu, P. Popescu, P. Banens, M. Copeland, G. Fortier, K. Howlett, M. Herod, D. Marchesan, Jonathan L. Showell, S. Sziiagyi, H. Tran, J. Weng
{"title":"Circuits and technologies for highly integrated optical networking ICs at 10 Gb/s to 40 Gb/s","authors":"S. Voinigescu, P. Popescu, P. Banens, M. Copeland, G. Fortier, K. Howlett, M. Herod, D. Marchesan, Jonathan L. Showell, S. Sziiagyi, H. Tran, J. Weng","doi":"10.1109/CICC.2001.929795","DOIUrl":"https://doi.org/10.1109/CICC.2001.929795","url":null,"abstract":"This paper presents a comparative overview of the performance of Si CMOS, SiGe BiCMOS and III-V HBT and FET technologies for 10-40 Gb/s fiber-optic applications. Active and passive device performance requirements, as well as on-chip isolation issues are first addressed. Fundamental building blocks are overviewed and the pros and cons of each technology implementation are discussed. Finally, a sub 2.5 W, highly integrated 10 Gb/s SiGe BiCMOS implementation of a 10 Gb/s to 622 Mb/s transceiver is described in detail. The transceiver achieves the highest level of integration, providing EOI (electro-optical-interface) and SerDes (Serializer-Deserializer) functions.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122129107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
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