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Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)最新文献

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Effects of non-uniform substrate temperature on the clock signal integrity in high performance designs 非均匀衬底温度对高性能设计中时钟信号完整性的影响
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929762
A. Ajami, Massoud Pedram, K. Banerjee
{"title":"Effects of non-uniform substrate temperature on the clock signal integrity in high performance designs","authors":"A. Ajami, Massoud Pedram, K. Banerjee","doi":"10.1109/CICC.2001.929762","DOIUrl":"https://doi.org/10.1109/CICC.2001.929762","url":null,"abstract":"This paper presents the analysis and modeling of the nonuniform substrate temperature in high performance ICs and its effect on the integrity of the clock signal. Using a novel non-uniform temperature-dependent distributed RC interconnect delay model, the behavior of clock skew in the presence of the substrate thermal gradients is analyzed and some design guidelines are provided to ensure the integrity of the clock signal.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"66 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114005712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
1.5 V 5.0 MHz switched capacitor circuits in 1.2 /spl mu/m CMOS without voltage bootstrapper 1.5 V 5.0 MHz开关电容电路，1.2 /spl mu/m CMOS，无电压启动器
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929715
Lei Wang, S. Embabi, E. Sánchez-Sinencio
{"title":"1.5 V 5.0 MHz switched capacitor circuits in 1.2 /spl mu/m CMOS without voltage bootstrapper","authors":"Lei Wang, S. Embabi, E. Sánchez-Sinencio","doi":"10.1109/CICC.2001.929715","DOIUrl":"https://doi.org/10.1109/CICC.2001.929715","url":null,"abstract":"A fully-differential switched capacitor (SC) bandpass biquad and a 4/sup th/ order bandpass /spl Delta/-/spl Sigma/ modulator were designed and fabricated in 1.2 /spl mu/m CMOS process. The supply voltage is 1.5 V without using any voltage bootstrapper. The clock frequency is 5.0 MHz in both circuits. The bandpass filter had Q=8.0 and IM3=-52 dB at its central frequency of 833 KHz. The 4/sup th/ order bandpass /spl Delta/-/spl Sigma/ modulator had SNR=61 dB and IM3<-78 dB in its narrowband of 25 KHz centered at the central frequency of 1.25 MHz.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"214 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116444618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Behavioral modeling of analog and mixed signal IC's: case studies of analog circuit simulation beyond SPICE 模拟和混合信号集成电路的行为建模:超越SPICE的模拟电路仿真案例研究
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929819
A. Abidi
{"title":"Behavioral modeling of analog and mixed signal IC's: case studies of analog circuit simulation beyond SPICE","authors":"A. Abidi","doi":"10.1109/CICC.2001.929819","DOIUrl":"https://doi.org/10.1109/CICC.2001.929819","url":null,"abstract":"Analog circuit designers trust SPICE because it represents a circuit in terms of the laws of physics governing each component. However, the increasing size of analog microsystems and the heterogeneity of waveform types of interest time-domain, frequency-domain, discrete-time, continuous-time-make it almost impossible to simulate these circuits efficiently on SPICE. Behavioral modeling offers one possible way to abstract the features of interest in a circuit block. Although simulation programs such as Saber have offered behavioral modeling for more than a decade, few seasoned analog circuit designers avail themselves of this capability. This paper describes how behavioral models were used in three state-of-the-art high performance mixed-signal design projects.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123803054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Solutions for highly integrated future generation software radio basestation transceivers 高度集成的下一代软件无线电基站收发器解决方案
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929832
A. Splett, H. Dressler, Armin Fuchs, R. Hofmann, B. Jelonnek, H. Kling, Eric Koenig, Anton Schultheiß
{"title":"Solutions for highly integrated future generation software radio basestation transceivers","authors":"A. Splett, H. Dressler, Armin Fuchs, R. Hofmann, B. Jelonnek, H. Kling, Eric Koenig, Anton Schultheiß","doi":"10.1109/CICC.2001.929832","DOIUrl":"https://doi.org/10.1109/CICC.2001.929832","url":null,"abstract":"This paper discusses transceiver technologies for future mobile radio basestations. Software radio technology places demanding requirements on both bandwidth and dynamic range of the transceiver technology, especially on the data converters. These requirements and a number of solution options are presented. Delta-sigma principles are favored to overcome bandwidth limitation. Recent progress in digital-to-analog converters is reported in which a multi-carrier CDMA signal can be directly converted to RF with sufficient dynamic range for 3/sup rd/ generation mobile communications systems.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123599820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A mixed-signal, functional level simulation framework based on SystemC for system-on-a-chip applications 一个基于SystemC的混合信号、功能级仿真框架，用于片上系统应用
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929838
T. E. Bonnerud, B. Hernes, T. Ytterdal
{"title":"A mixed-signal, functional level simulation framework based on SystemC for system-on-a-chip applications","authors":"T. E. Bonnerud, B. Hernes, T. Ytterdal","doi":"10.1109/CICC.2001.929838","DOIUrl":"https://doi.org/10.1109/CICC.2001.929838","url":null,"abstract":"In this paper, we describe a mixed-signal simulation framework based on the SystemC C++ class libraries. By adding an analog extension to SystemC, we have developed a modular functional level simulation environment that achieves comparable accuracy to MATLAB. We illustrate the usability of the framework by presenting the results of an investigation of the properties of a background calibration technique for pipelined analog-to-digital converters.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127348036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
CMOS process compatible ie-Flash (inverse gate electrode Flash) technology for system-on-a-chip 适用于片上系统的CMOS工艺兼容ie-Flash(反栅电极Flash)技术
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929750
S. Shukuri, K. Yanagisawa, K. Ishibashi
{"title":"CMOS process compatible ie-Flash (inverse gate electrode Flash) technology for system-on-a-chip","authors":"S. Shukuri, K. Yanagisawa, K. Ishibashi","doi":"10.1109/CICC.2001.929750","DOIUrl":"https://doi.org/10.1109/CICC.2001.929750","url":null,"abstract":"A highly reliable single-poly flash technology named ie-Flash (inverse gate electrode Flash), which can be embedded in the common 0.14 /spl mu/m CMOS process without any process modifications, has been developed. The ie-Flash cell consists of two elementary cells for OR-logical reading, resulting in significant improvement of reliability. 5 V programming with 1 ms duration and 1.2 V-read operation of 35 bit memory modules fabricated by a 0.14 /spl mu/m CMOS process is demonstrated.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128839766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 3.3 V transconductor in 0.35 /spl mu/m CMOS with 80 dB SFDR up to 10 MHz 一个3.3 V的晶体管，0.35 /spl mu/m CMOS, 80db SFDR高达10 MHz
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929822
U. Chilakapati, T. Fiez, A. Eshraghi
{"title":"A 3.3 V transconductor in 0.35 /spl mu/m CMOS with 80 dB SFDR up to 10 MHz","authors":"U. Chilakapati, T. Fiez, A. Eshraghi","doi":"10.1109/CICC.2001.929822","DOIUrl":"https://doi.org/10.1109/CICC.2001.929822","url":null,"abstract":"A CMOS transconductor uses resistors at the input and an OTA in unity-gain feedback to achieve 80 dB SFDR for 3.6 V/sub pp/ differential inputs up to 10 MHz. The transconductance core dissipates 10.56 mW from a 3.3 V supply and occupies 0.4 mm/sup 2/ in a 0.35 /spl mu/m CMOS process.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122127772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A completely integrated 2 GHz VCO with post-processed Cu inductors 一个完全集成的2 GHz压控振荡器与后处理铜电感
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929845
J. Rogers, V. Levenets, C. Pawlowicz, N. G. Tarr, T. Smy, C. Plett
{"title":"A completely integrated 2 GHz VCO with post-processed Cu inductors","authors":"J. Rogers, V. Levenets, C. Pawlowicz, N. G. Tarr, T. Smy, C. Plett","doi":"10.1109/CICC.2001.929845","DOIUrl":"https://doi.org/10.1109/CICC.2001.929845","url":null,"abstract":"A simple post-processing technique allowing Cu inductors to be added to integrated circuits is presented. The inductors use a 4 /spl mu/m thick Cu layer, and are formed over a 9 /spl mu/m thick polyimide dielectric. VCOs with Cu inductors gave a phase noise of -106 dBc/Hz at 100 kHz offset from a 2 GHz carrier. In contrast, an identical control circuit with Al inductors gave a phase noise of only -101 dBc/Hz at 100 kHz offset from a 1.8 GHz carrier and had higher power consumption.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130207499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Test-circuit-based extraction of inter- and intra-chip MOSFET-performance variations for analog-design reliability 基于测试电路的芯片间和芯片内mosfet性能变化提取模拟设计可靠性
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929801
S. Matsumoto, H. Mattausch, S. Ooshiro, Y. Tatsumi, M. Miura-Mattausch, S. Kumashiro, Terufumi Yamaguchi, K. Yamashita, N. Nakayama
{"title":"Test-circuit-based extraction of inter- and intra-chip MOSFET-performance variations for analog-design reliability","authors":"S. Matsumoto, H. Mattausch, S. Ooshiro, Y. Tatsumi, M. Miura-Mattausch, S. Kumashiro, Terufumi Yamaguchi, K. Yamashita, N. Nakayama","doi":"10.1109/CICC.2001.929801","DOIUrl":"https://doi.org/10.1109/CICC.2001.929801","url":null,"abstract":"We propose an efficient, test-circuit-based method to determine not only CMOS-device-parameter variations but to simultaneously separate intra-chip from inter-chip variations. The method is demonstrated by using a differential-amplifier stage with feedback coupling as the test-circuit and the drift-diffusion MOSFET model HiSIM for the circuit simulation. The result shows that the proposed test circuit, when constructed only with n-MOSFETs or p-MOSFETs, enables one to separate gate length and channel doping variations as well as their inter- and intra-chip magnitudes in a direct way.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130495182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Low-cost, software-based self-test methodologies for performance faults in processor control subsystems 处理器控制子系统中性能故障的低成本、基于软件的自检方法
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929769
S. Almukhaizim, Peter Petrov, A. Orailoglu
{"title":"Low-cost, software-based self-test methodologies for performance faults in processor control subsystems","authors":"S. Almukhaizim, Peter Petrov, A. Orailoglu","doi":"10.1109/CICC.2001.929769","DOIUrl":"https://doi.org/10.1109/CICC.2001.929769","url":null,"abstract":"A software-based testing methodology for processor control subsystems, targeting hard-to-test performance faults in high-end embedded and general-purpose processors, is presented. An algorithm for directly controlling, using the instruction-set architecture only, the branch-prediction logic, a representative example of the class of processor control subsystems particularly prone to such performance faults, is outlined. Experimental results confirm the viability of the proposed methodology as a low-cost and effective answer to the problem of hard-to-test performance faults in processor architectures.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129950149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
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