一个3.3 V的晶体管，0.35 /spl mu/m CMOS, 80db SFDR高达10 MHz

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI:10.1109/CICC.2001.929822

U. Chilakapati, T. Fiez, A. Eshraghi

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引用次数: 1

摘要

CMOS晶体管在输入端使用电阻，在单位增益反馈中使用OTA，在高达10mhz的3.6 V/sub /差分输入下实现80db SFDR。跨导磁芯在3.3 V电源下耗散10.56 mW，在0.35 /spl mu/m CMOS工艺中占用0.4 mm/sup / 2/。

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A 3.3 V transconductor in 0.35 /spl mu/m CMOS with 80 dB SFDR up to 10 MHz

A CMOS transconductor uses resistors at the input and an OTA in unity-gain feedback to achieve 80 dB SFDR for 3.6 V/sub pp/ differential inputs up to 10 MHz. The transconductance core dissipates 10.56 mW from a 3.3 V supply and occupies 0.4 mm/sup 2/ in a 0.35 /spl mu/m CMOS process.

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Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)

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