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Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)最新文献

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A 2.4-GHz, 2.2-W, 2-V fully-integrated CMOS circular-geometry active-transformer power amplifier 一种2.4 ghz, 2.2 w, 2v全集成CMOS圆几何有源变压器功率放大器
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-09 DOI: 10.1109/CICC.2001.929723
I. Aoki, S. Kee, D. Rutledge, A. Hajimiri
{"title":"A 2.4-GHz, 2.2-W, 2-V fully-integrated CMOS circular-geometry active-transformer power amplifier","authors":"I. Aoki, S. Kee, D. Rutledge, A. Hajimiri","doi":"10.1109/CICC.2001.929723","DOIUrl":"https://doi.org/10.1109/CICC.2001.929723","url":null,"abstract":"A 2.4-GHz, 2.2-W, 2-V fully integrated circular geometry power amplifier with 50 /spl Omega/ input and output matching is fabricated using 2.5 V, 0.35 /spl mu/m CMOS transistors. It can also produce 450 mW using a 1 V supply. Harmonic suppression is 64 dB or better. An on-chip circular-geometry active-transformer is used to combine several push-pull low-voltage amplifiers efficiently to produce a larger output power while maintaining a 50 /spl Omega/ match. This new on-chip power combining and impedance matching method uses virtual AC grounds and magnetic couplings extensively to eliminate the need for any offchip component such as wirebonds. It also desensitizes the operation of the amplifier to the inductance of bonding wires and makes the design more reproducible. This new topology makes possible a fully-integrated 2.2 W, 2.4 GHz, low voltage CMOS power amplifier for the first time.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116616873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 43
A CMOS VLSI delay oriented waveform converter dedicated to the synthesizer of an UMTS transceiver 专用于UMTS收发器合成器的CMOS VLSI面向延迟的波形转换器
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-09 DOI: 10.1109/CICC.2001.929759
Anne Spataro, Y. Deval, Jean-Baptiste Bigueret, P. Fouillat, D. Belot
{"title":"A CMOS VLSI delay oriented waveform converter dedicated to the synthesizer of an UMTS transceiver","authors":"Anne Spataro, Y. Deval, Jean-Baptiste Bigueret, P. Fouillat, D. Belot","doi":"10.1109/CICC.2001.929759","DOIUrl":"https://doi.org/10.1109/CICC.2001.929759","url":null,"abstract":"In this paper we present a waveform converter implemented on a 0.25 /spl mu/m CMOS technology using a dedicated design methodology (delay oriented design). The circuit converts a square wave signal in both in-phase and quadrature-phase sinusoidal differential outputs. It also multiplies the frequency by seven. The output frequency range of this converter extends from 1.05 GHz up to 2.17 GHz. This converter is dedicated for the design of a third generation mobile phone synthesizer using a double loop architecture. For an output frequency of 2 GHz, the measured phase noise at 10 kHz offset from the carrier is -97 dBc/Hz. The circuit consumes 50 mW from a 2.5 V supply.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122963303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Implementation of a Hermitian decoder IC in 0.35 /spl mu/m CMOS 在0.35 /spl mu/m CMOS中实现厄米解码器IC
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-09 DOI: 10.1109/CICC.2001.929782
J. B. Ashbrook, Naresh R Shanbhag, R. Koetter, R. Blahut
{"title":"Implementation of a Hermitian decoder IC in 0.35 /spl mu/m CMOS","authors":"J. B. Ashbrook, Naresh R Shanbhag, R. Koetter, R. Blahut","doi":"10.1109/CICC.2001.929782","DOIUrl":"https://doi.org/10.1109/CICC.2001.929782","url":null,"abstract":"This paper presents the first integrated circuit implementation of\u0000a Hermitian decoder thereby proving its practical viability. Hermitian\u0000codes provide much larger block lengths (n=4080) compared to that of the\u0000popular Reed-Solomon (RS) codes (n=256) over the same field (GF(256)).\u0000This translates to a coding gain of 0.6 dB for the same rate. However,\u0000Hermitian codes were deemed to be too complex to implement until the\u0000emergence of a recent algorithmic breakthrough which made the complexity\u0000of Hermitian decoders comparable to that of RS codes. Based on Koetter's\u0000decoding algorithm, the chip architecture consists of an array of\u0000sixteen interdependent Berlekamp-Massey algorithm (BMA) blocks. Thus,\u0000the same IC can be used for decoding RS codes as well. The decoder IC is\u0000designed in a 3.3 V, 0.35 μm, four-metal CMOS process and can correct\u0000up to t=60 errors per block of n=4080 words at a rate of 400 Mb/s. The\u0000IC prototype consumes 3.0 W with a 50 MHz clock","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128964057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
ESD protection device issues for IC designs IC设计中的ESD保护器件问题
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-09 DOI: 10.1109/CICC.2001.929720
C. Duvvury
{"title":"ESD protection device issues for IC designs","authors":"C. Duvvury","doi":"10.1109/CICC.2001.929720","DOIUrl":"https://doi.org/10.1109/CICC.2001.929720","url":null,"abstract":"Electrostatic discharge (ESD) has been a major concern for IC chip quality. In this paper, the IC damage phenomena due to ESD and the protection techniques are reviewed. Also, the severe impact of the advanced process technologies on the ESD robustness, and the special circuit requirements that make the protection design even more challenging will be addressed. The recently developed simulation and modeling methods to improve the protection designs are also discussed.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134353851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A 2.2 GHz CMOS VCO with inductive degeneration noise suppression 一种具有电感退化噪声抑制的2.2 GHz CMOS压控振荡器
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-09 DOI: 10.1109/CICC.2001.929754
P. Andreani, H. Sjöland
{"title":"A 2.2 GHz CMOS VCO with inductive degeneration noise suppression","authors":"P. Andreani, H. Sjöland","doi":"10.1109/CICC.2001.929754","DOIUrl":"https://doi.org/10.1109/CICC.2001.929754","url":null,"abstract":"A 1.4 V, 9 mA monolithic LC-tank voltage-controlled oscillator (VCO) fabricated in a standard 0.35 /spl mu/m CMOS process is presented. The VCO is tunable between 2.0 GHz and 2.37 GHz, and displays a phase noise between -140 dBc/Hz and -138 dBc/Hz at a 3 MHz offset frequency across the whole tuning range. This low phase noise is achieved through the use of an on-chip LC filter and an off-chip low frequency inductor, which totally remove the noise of the tail current source. The phase noise improvement due to the off-chip inductor is between 2 dB and 6 dB, increasing with higher oscillation frequencies.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"252 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117301026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 50
A DSP based 10BaseT/100BaseTX Ethernet transceiver in a 1.8 V, 0.18 /spl mu/m CMOS technology 基于DSP的10BaseT/100BaseTX以太网收发器，采用1.8 V, 0.18 /spl mu/m CMOS技术
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-09 DOI: 10.1109/CICC.2001.929741
S. Huss, M. Mullen, C. T. Gray, Randall Smith, M. Summers, J. Shafer, Pat Heron, Tim Sawinska, Joe Medero
{"title":"A DSP based 10BaseT/100BaseTX Ethernet transceiver in a 1.8 V, 0.18 /spl mu/m CMOS technology","authors":"S. Huss, M. Mullen, C. T. Gray, Randall Smith, M. Summers, J. Shafer, Pat Heron, Tim Sawinska, Joe Medero","doi":"10.1109/CICC.2001.929741","DOIUrl":"https://doi.org/10.1109/CICC.2001.929741","url":null,"abstract":"This paper describes a DSP based 10BaseT/100BaseTX Ethernet physical layer interface in a 1.8, V 0.18 /spl mu/m single-poly 5-level metal CMOS technology. The DSP architecture allows for robust performance for cable lengths >150 m. The integrated transceiver is IEEE 802.3 compliant and uses existing 1:1 transformers. The active area is 6.6 mm/sup 2/ and consumes 350 mW of power.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116130593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Methodology of self-heating free parameter extraction and circuit simulation for SOI CMOS SOI CMOS自热自由参数提取方法及电路仿真
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-09 DOI: 10.1109/CICC.2001.929805
H. Nakayama, P. Su, C. Hu, M. Nakamura, H. Komatsu, K. Takeshita, Y. Komatsu
{"title":"Methodology of self-heating free parameter extraction and circuit simulation for SOI CMOS","authors":"H. Nakayama, P. Su, C. Hu, M. Nakamura, H. Komatsu, K. Takeshita, Y. Komatsu","doi":"10.1109/CICC.2001.929805","DOIUrl":"https://doi.org/10.1109/CICC.2001.929805","url":null,"abstract":"Novel SOI (Silicon On Insulator) model parameter extraction methodology based on the concept of SHE (Self-Heating Effect) free device modeling, is proposed and demonstrated for a 0.18 /spl mu/m PD (Partially Depleted) SOI technology. In this methodology, prior to SPICE parameter extraction, the device thermal resistances are measured and the current loss due to SHE is added back analytically to DC I-V data. Therefore, the parameters are free from SHE. DC, AC, and transient simulation results using this technology show good agreement with measurement data.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132598516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A 105 dB SNR multibit /spl Sigma//spl Delta/ ADC for digital audio applications 用于数字音频应用的105 dB信噪比多位/spl Sigma//spl Delta/ ADC
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-09 DOI: 10.1109/CICC.2001.929717
K. Nguyen, B. Adams, K. Sweetland
{"title":"A 105 dB SNR multibit /spl Sigma//spl Delta/ ADC for digital audio applications","authors":"K. Nguyen, B. Adams, K. Sweetland","doi":"10.1109/CICC.2001.929717","DOIUrl":"https://doi.org/10.1109/CICC.2001.929717","url":null,"abstract":"A four-channel multibit /spl Sigma//spl Delta/ analog-to-digital converter (ADC) for consumer audio applications is described. The converter uses a second order switched-capacitor modulator with a 4-bit quantizer and a noise-shaped scrambler for dynamic element matching. To achieve the target settling time with reduced power consumption, the opamps are dynamically compensated. A multi-stage decimation filter with adjustable front-end sine filter is used to produce the PCM output at a selectable sample rate of 48/96 kHz. The converter achieves an SNR and D-range of 105 dB (A-weighted), THD+N of -98 dB at 48 kHz sample rate. The circuit is implemented in 0.5 /spl mu/m DPTM CMOS, dissipating 90 mW per channels. The core die size is 1.6 mm/sup 2/ per channel.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131149592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Capacity limits and matching properties of lateral flux integrated capacitors 横向磁通集成电容器的容量限制和匹配特性
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-09 DOI: 10.1109/CICC.2001.929803
R. Aparicio, A. Hajimiri
{"title":"Capacity limits and matching properties of lateral flux integrated capacitors","authors":"R. Aparicio, A. Hajimiri","doi":"10.1109/CICC.2001.929803","DOIUrl":"https://doi.org/10.1109/CICC.2001.929803","url":null,"abstract":"Theoretical limits for the capacitance density of lateral flux and quasi-fractal capacitors are calculated. These limits are used to investigate the efficiency of various capacitive structures such as lateral flux and quasi-fractal structures. This study leads to two new capacitor structures with high lateral field efficiency. Simulation and experimental results demonstrate higher capacity and superior matching properties compared to the standard horizontal parallel plate and previously reported lateral-field capacitors.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132729384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Automatic amplitude control loop for a 2-V, 2.5-GHz LC-tank VCO 用于2v, 2.5 ghz LC-tank VCO的自动幅度控制回路
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-09 DOI: 10.1109/CICC.2001.929757
A. Zanchi, A. Bonfanti, S. Levantino, C. Samori, A. Lacaita
{"title":"Automatic amplitude control loop for a 2-V, 2.5-GHz LC-tank VCO","authors":"A. Zanchi, A. Bonfanti, S. Levantino, C. Samori, A. Lacaita","doi":"10.1109/CICC.2001.929757","DOIUrl":"https://doi.org/10.1109/CICC.2001.929757","url":null,"abstract":"The paper discusses the design of the automatic amplitude control circuit (AAC) for wireless-targeted oscillators, presenting a 2-V, 2.5-GHz LC-tank bipolar VCO. Potential phase noise degradation due to the amplitude loop is illustrated, along with design choices to avoid this effect. The circuit manufactured draws 7 mA in the VCO and less than 600 μA in the AAC, with SSCR=-104 dBc/Hz@100 kHz. Once normalized for power, Q-factor and operating frequency, this phase noise performance ranks first among the bipolar VCOs published so far.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"158 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116270004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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