{"title":"用于数字音频应用的105 dB信噪比多位/spl Sigma//spl Delta/ ADC","authors":"K. Nguyen, B. Adams, K. Sweetland","doi":"10.1109/CICC.2001.929717","DOIUrl":null,"url":null,"abstract":"A four-channel multibit /spl Sigma//spl Delta/ analog-to-digital converter (ADC) for consumer audio applications is described. The converter uses a second order switched-capacitor modulator with a 4-bit quantizer and a noise-shaped scrambler for dynamic element matching. To achieve the target settling time with reduced power consumption, the opamps are dynamically compensated. A multi-stage decimation filter with adjustable front-end sine filter is used to produce the PCM output at a selectable sample rate of 48/96 kHz. The converter achieves an SNR and D-range of 105 dB (A-weighted), THD+N of -98 dB at 48 kHz sample rate. The circuit is implemented in 0.5 /spl mu/m DPTM CMOS, dissipating 90 mW per channels. The core die size is 1.6 mm/sup 2/ per channel.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 105 dB SNR multibit /spl Sigma//spl Delta/ ADC for digital audio applications\",\"authors\":\"K. Nguyen, B. Adams, K. Sweetland\",\"doi\":\"10.1109/CICC.2001.929717\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A four-channel multibit /spl Sigma//spl Delta/ analog-to-digital converter (ADC) for consumer audio applications is described. The converter uses a second order switched-capacitor modulator with a 4-bit quantizer and a noise-shaped scrambler for dynamic element matching. To achieve the target settling time with reduced power consumption, the opamps are dynamically compensated. A multi-stage decimation filter with adjustable front-end sine filter is used to produce the PCM output at a selectable sample rate of 48/96 kHz. The converter achieves an SNR and D-range of 105 dB (A-weighted), THD+N of -98 dB at 48 kHz sample rate. The circuit is implemented in 0.5 /spl mu/m DPTM CMOS, dissipating 90 mW per channels. The core die size is 1.6 mm/sup 2/ per channel.\",\"PeriodicalId\":101717,\"journal\":{\"name\":\"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-05-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2001.929717\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2001.929717","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 105 dB SNR multibit /spl Sigma//spl Delta/ ADC for digital audio applications
A four-channel multibit /spl Sigma//spl Delta/ analog-to-digital converter (ADC) for consumer audio applications is described. The converter uses a second order switched-capacitor modulator with a 4-bit quantizer and a noise-shaped scrambler for dynamic element matching. To achieve the target settling time with reduced power consumption, the opamps are dynamically compensated. A multi-stage decimation filter with adjustable front-end sine filter is used to produce the PCM output at a selectable sample rate of 48/96 kHz. The converter achieves an SNR and D-range of 105 dB (A-weighted), THD+N of -98 dB at 48 kHz sample rate. The circuit is implemented in 0.5 /spl mu/m DPTM CMOS, dissipating 90 mW per channels. The core die size is 1.6 mm/sup 2/ per channel.