Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)最新文献

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Capacity limits and matching properties of lateral flux integrated capacitors 横向磁通集成电容器的容量限制和匹配特性
R. Aparicio, A. Hajimiri
{"title":"Capacity limits and matching properties of lateral flux integrated capacitors","authors":"R. Aparicio, A. Hajimiri","doi":"10.1109/CICC.2001.929803","DOIUrl":"https://doi.org/10.1109/CICC.2001.929803","url":null,"abstract":"Theoretical limits for the capacitance density of lateral flux and quasi-fractal capacitors are calculated. These limits are used to investigate the efficiency of various capacitive structures such as lateral flux and quasi-fractal structures. This study leads to two new capacitor structures with high lateral field efficiency. Simulation and experimental results demonstrate higher capacity and superior matching properties compared to the standard horizontal parallel plate and previously reported lateral-field capacitors.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132729384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Automatic amplitude control loop for a 2-V, 2.5-GHz LC-tank VCO 用于2v, 2.5 ghz LC-tank VCO的自动幅度控制回路
A. Zanchi, A. Bonfanti, S. Levantino, C. Samori, A. Lacaita
{"title":"Automatic amplitude control loop for a 2-V, 2.5-GHz LC-tank VCO","authors":"A. Zanchi, A. Bonfanti, S. Levantino, C. Samori, A. Lacaita","doi":"10.1109/CICC.2001.929757","DOIUrl":"https://doi.org/10.1109/CICC.2001.929757","url":null,"abstract":"The paper discusses the design of the automatic amplitude control circuit (AAC) for wireless-targeted oscillators, presenting a 2-V, 2.5-GHz LC-tank bipolar VCO. Potential phase noise degradation due to the amplitude loop is illustrated, along with design choices to avoid this effect. The circuit manufactured draws 7 mA in the VCO and less than 600 μA in the AAC, with SSCR=-104 dBc/Hz@100 kHz. Once normalized for power, Q-factor and operating frequency, this phase noise performance ranks first among the bipolar VCOs published so far.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"158 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116270004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A transimpedance amplifier with DC-coupled differential photodiode current sensing for wireless optical communications 一种用于无线光通信的带直流耦合差分光电二极管电流传感的透阻放大器
B. Zand, K. Phang, D. Johns
{"title":"A transimpedance amplifier with DC-coupled differential photodiode current sensing for wireless optical communications","authors":"B. Zand, K. Phang, D. Johns","doi":"10.1109/CICC.2001.929821","DOIUrl":"https://doi.org/10.1109/CICC.2001.929821","url":null,"abstract":"A transimpedance amplifier with differential DC-coupled photocurrent sensing was integrated in a standard 0.35 /spl mu/m CMOS process. It achieves 33 k/spl Omega/ transimpedance gain and a bandwidth of 255 MHz with a 2 pF photodiode capacitance. This design exhibits 40 dB power supply rejection ratio and an average input noise of (6.8pA)/(/spl radic/Hz). Power dissipation is 30 mW from a 3 V supply.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122020222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Driving CMOS into the wireless communications arena with technology scaling 以技术规模驱动CMOS进入无线通信领域
K. Chew, S. Chu, Che-Choi Leung
{"title":"Driving CMOS into the wireless communications arena with technology scaling","authors":"K. Chew, S. Chu, Che-Choi Leung","doi":"10.1109/CICC.2001.929844","DOIUrl":"https://doi.org/10.1109/CICC.2001.929844","url":null,"abstract":"This paper provides a review of the impact of technology scaling on the radio-frequency (RF) performance of CMOS devices. The major active and passive elements are presented. Unity current gain frequency and unity power gain frequency of greater than 50 GHz and 60 GHz respectively have been achieved with the 180 nm transistors. The minimum noise figure is less than 1.5 dB at 2.45 GHz for gate lengths of 250 nm and below. The flicker noise spectra of thin- and thick-gate transistors have risen by an order of magnitude due to the effects of scaling and nitridation. Quality factors (Q) close to 10 and Q-enhancement of greater than 50% at 2.45 GHz have been achieved using 2 /spl mu/m thick top aluminimum metal on circular stacked coil inductors.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115321308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A shared built-in self-repair analysis for multiple embedded memories 为多个嵌入式存储器提供共享的内置自我修复分析
J. Ohtani, T. Ooishi, T. Kawagoe, M. Niiro, M. Maruta, H. Hidaka
{"title":"A shared built-in self-repair analysis for multiple embedded memories","authors":"J. Ohtani, T. Ooishi, T. Kawagoe, M. Niiro, M. Maruta, H. Hidaka","doi":"10.1109/CICC.2001.929752","DOIUrl":"https://doi.org/10.1109/CICC.2001.929752","url":null,"abstract":"A shared built-in self-repair analysis scheme (Shared-BISA) for multiple embedded memory cores in the SOC is proposed to realize minimum area penalty independent of the number of embedded memory cores. A compact reconfigurable CAM array in the BISA circuitry realizes a flexible redundancy analysis structure to cope with various memory core and redundancy structures, and a high-speed operation up to 500 MHz.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122432747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 12 mW ADC delta-sigma modulator with 80 dB of dynamic range integrated in a single-chip Bluetooth transceiver 在单芯片蓝牙收发器中集成了一个动态范围为80db的12mw ADC delta-sigma调制器
J. Grilo, I. Galton, Kevin J. Wang, R. Montemayor
{"title":"A 12 mW ADC delta-sigma modulator with 80 dB of dynamic range integrated in a single-chip Bluetooth transceiver","authors":"J. Grilo, I. Galton, Kevin J. Wang, R. Montemayor","doi":"10.1109/CICC.2001.929716","DOIUrl":"https://doi.org/10.1109/CICC.2001.929716","url":null,"abstract":"A 12 mW switched-capacitor (SC) multi-bit ADC delta-sigma modulator for baseband demodulation integrated in a single-chip Bluetooth radio-modem transceiver achieves 77 dB of SINAD and 80 dB of dynamic range over a 500 kHz bandwidth with a 32 MHz sample-rate. The 1 mm/sup 2/ circuit is implemented in a 0.35 /spl mu/m BiCMOS SOI process and operates from a 2.7 V supply.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"2017 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121867118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 56
A 0.9 V, 0.51 /spl mu/A rail-to-rail CMOS operational amplifier 一个0.9 V, 0.51 /spl μ A的轨对轨CMOS运算放大器
T. Stockstad, H. Yoshizawa
{"title":"A 0.9 V, 0.51 /spl mu/A rail-to-rail CMOS operational amplifier","authors":"T. Stockstad, H. Yoshizawa","doi":"10.1109/CICC.2001.929824","DOIUrl":"https://doi.org/10.1109/CICC.2001.929824","url":null,"abstract":"A 0.9 V, 0.5 /spl mu/A, rail-to-rail CMOS operational amplifier designed with weak inversion techniques is presented. Depletion-mode NMOS transistors buffer a bulk-driven PMOS differential pair to realize wide input dynamic range, while the output stage architecture provides symmetric rail-to-rail output drive through the use of a low voltage translinear control circuit.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126905149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
A multicarrier QAM-modulator for WCDMA basestation with on-chip D/A converter 带片上D/A转换器的WCDMA基站多载波qam调制器
M. Kosunen, J. Vankka, M. Waltari, K. Halonen
{"title":"A multicarrier QAM-modulator for WCDMA basestation with on-chip D/A converter","authors":"M. Kosunen, J. Vankka, M. Waltari, K. Halonen","doi":"10.1109/CICC.2001.929784","DOIUrl":"https://doi.org/10.1109/CICC.2001.929784","url":null,"abstract":"A multicarrier QAM modulator for a wideband code division multiple access (WCDMA) basestation has been designed. The multicarrier modulator performs pulse shaping filtering for four baseband I and Q data streams. Input data is interpolated in four stages each interpolating by a factor two. Four independent carriers are generated and modulated with the CORDIC based numerically controlled oscillators (NCOs) and summed up to form a multicarrier WCDMA signal. SINC-attenuation effect of a D/A converter is canceled by an inverse-SINC predistortion filter. The multicarrier signal is converted to the analog domain with a 14-bit current steering D/A converter which is integrated on the same silicon chip. Process used in realization of the chip is a 0.35 /spl mu/m BiCMOS process. However, only CMOS transistors are used.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121417685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Shared data line technique for doubling the data transfer rate per pin of differential interfaces 将差分接口的每个引脚的数据传输速率加倍的共享数据线技术
F. Hatori, S. Kousai, Y. Unekawa
{"title":"Shared data line technique for doubling the data transfer rate per pin of differential interfaces","authors":"F. Hatori, S. Kousai, Y. Unekawa","doi":"10.1109/CICC.2001.929830","DOIUrl":"https://doi.org/10.1109/CICC.2001.929830","url":null,"abstract":"A technique for almost doubling the data transfer rate per pin of the differential interfaces has been proposed. In this technique the number of the differential transmission lines between transmitter LSI and the receiver LSI are shared with adjacent buffers to increase the transfer rate per pin. Each receiver consists of two comparators and a decoder circuit translates the signal voltage at the receiver end of the transmission line into digital data. A data rate of 1.1 Gbps/pin has been achieved in the fabricated test circuit in CMOS technology.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127734452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A fast method for identifying matching-relevant transistor pairs 一种快速识别匹配相关晶体管对的方法
F. Schenkel, M. Pronath, H. Graeb, K. Antreich
{"title":"A fast method for identifying matching-relevant transistor pairs","authors":"F. Schenkel, M. Pronath, H. Graeb, K. Antreich","doi":"10.1109/CICC.2001.929802","DOIUrl":"https://doi.org/10.1109/CICC.2001.929802","url":null,"abstract":"This paper presents a new method to identify mismatch-relevant transistor pairs at the circuit level. It consists in a two-stage selection process that is derived from a sensitivity-based formulation of matching relevancy and is thus very fast. The presented results show the efficiency and effectiveness of the method.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125478869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
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