{"title":"一个0.9 V, 0.51 /spl μ A的轨对轨CMOS运算放大器","authors":"T. Stockstad, H. Yoshizawa","doi":"10.1109/CICC.2001.929824","DOIUrl":null,"url":null,"abstract":"A 0.9 V, 0.5 /spl mu/A, rail-to-rail CMOS operational amplifier designed with weak inversion techniques is presented. Depletion-mode NMOS transistors buffer a bulk-driven PMOS differential pair to realize wide input dynamic range, while the output stage architecture provides symmetric rail-to-rail output drive through the use of a low voltage translinear control circuit.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"35","resultStr":"{\"title\":\"A 0.9 V, 0.51 /spl mu/A rail-to-rail CMOS operational amplifier\",\"authors\":\"T. Stockstad, H. Yoshizawa\",\"doi\":\"10.1109/CICC.2001.929824\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 0.9 V, 0.5 /spl mu/A, rail-to-rail CMOS operational amplifier designed with weak inversion techniques is presented. Depletion-mode NMOS transistors buffer a bulk-driven PMOS differential pair to realize wide input dynamic range, while the output stage architecture provides symmetric rail-to-rail output drive through the use of a low voltage translinear control circuit.\",\"PeriodicalId\":101717,\"journal\":{\"name\":\"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)\",\"volume\":\"54 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-05-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"35\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2001.929824\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2001.929824","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 0.9 V, 0.51 /spl mu/A rail-to-rail CMOS operational amplifier
A 0.9 V, 0.5 /spl mu/A, rail-to-rail CMOS operational amplifier designed with weak inversion techniques is presented. Depletion-mode NMOS transistors buffer a bulk-driven PMOS differential pair to realize wide input dynamic range, while the output stage architecture provides symmetric rail-to-rail output drive through the use of a low voltage translinear control circuit.