为多个嵌入式存储器提供共享的内置自我修复分析

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI:10.1109/CICC.2001.929752

J. Ohtani, T. Ooishi, T. Kawagoe, M. Niiro, M. Maruta, H. Hidaka

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引用次数: 10

摘要

提出了一种针对SOC中多个嵌入式存储核的共享内置自修复分析方案(shared - bisa)，以实现与嵌入式存储核数无关的最小面积损失。BISA电路中的可重构CAM阵列实现了灵活的冗余分析结构，以应对各种存储核心和冗余结构，并实现了高达500 MHz的高速运行。

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A shared built-in self-repair analysis for multiple embedded memories

A shared built-in self-repair analysis scheme (Shared-BISA) for multiple embedded memory cores in the SOC is proposed to realize minimum area penalty independent of the number of embedded memory cores. A compact reconfigurable CAM array in the BISA circuitry realizes a flexible redundancy analysis structure to cope with various memory core and redundancy structures, and a high-speed operation up to 500 MHz.

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Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)

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