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Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)最新文献

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Interface socket design methodology to generate embedded DRAM macros 生成嵌入式DRAM宏的接口套接字设计方法
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929837
R. Haga, T. Kaneko, A. Nakayama, S. Miyano, H. Takenaka, K. Numata, Hiroyuki Koinuma, T. Hojo, A. Sato, T. Kouchi, K. Mimoto, M. Tazawa, T. Ohkubo, T. Andou, T. Amano
{"title":"Interface socket design methodology to generate embedded DRAM macros","authors":"R. Haga, T. Kaneko, A. Nakayama, S. Miyano, H. Takenaka, K. Numata, Hiroyuki Koinuma, T. Hojo, A. Sato, T. Kouchi, K. Mimoto, M. Tazawa, T. Ohkubo, T. Andou, T. Amano","doi":"10.1109/CICC.2001.929837","DOIUrl":"https://doi.org/10.1109/CICC.2001.929837","url":null,"abstract":"A new design methodology for embedded DRAM is introduced. The DRAM macro consists of common DRAM core and interface socket. Splitting the DRAM macro into common DRAM core and interface socket widens the reconfigurability of the functions of the macro. An experimental chip consists of 12M-bit DRAM core and synchronous interface socket was developed with 0.18 /spl mu/m technology.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115807401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 99-mm/sup 2/, 0.7-W, single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mbit embedded DRAM for portable 422P@HL encoder system 一个99毫米/sup 2/， 0.7 w，单片MPEG-2 422P@ML视频，音频和系统编码器与64兆嵌入式DRAM便携式422P@HL编码器系统
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929815
Satoshi Kumaki, H. Takata, Y. Ajioka, T. Ooishi, K. Ishihara, A. Hanami, Takaharu Tsuji, Tetsuya Watanabe, C. Morishima, T. Yoshizawa, Hidenori Sato, S. Hattori, A. Koshio, K. Tsukamoto, T. Matsumura
{"title":"A 99-mm/sup 2/, 0.7-W, single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mbit embedded DRAM for portable 422P@HL encoder system","authors":"Satoshi Kumaki, H. Takata, Y. Ajioka, T. Ooishi, K. Ishihara, A. Hanami, Takaharu Tsuji, Tetsuya Watanabe, C. Morishima, T. Yoshizawa, Hidenori Sato, S. Hattori, A. Koshio, K. Tsukamoto, T. Matsumura","doi":"10.1109/CICC.2001.929815","DOIUrl":"https://doi.org/10.1109/CICC.2001.929815","url":null,"abstract":"A scalable single-chip 422P@ML MPEG-2 video, audio, and system encoder LSI for portable 422P@HL system is described. The encoder LSI is implemented using 0.13 /spl mu/m embedded DRAM technology. It integrates 3-M logic gates and 64-Mbit DRAM in an area of 99-mm/sup 2/. The power consumption is suppressed to 0.7-Watts by adopting a low power DRAM core. It performs real-time 422P@ML video encoding, audio encoding, and system encoding with no external DRAM. Furthermore, the encoder LSI realizes a 422P@HL video encoder with multi-chip configuration, due to its scalable architecture. This results in a PC-card size 422P@HL encoder with lowest power consumption for portable HDTV codec system.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133481473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Accurate prediction of spectral regrowth and in-channel distortion based on CDMA signal time-domain model 基于CDMA信号时域模型的频谱再生和信道内失真的精确预测
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929722
V. Aparin
{"title":"Accurate prediction of spectral regrowth and in-channel distortion based on CDMA signal time-domain model","authors":"V. Aparin","doi":"10.1109/CICC.2001.929722","DOIUrl":"https://doi.org/10.1109/CICC.2001.929722","url":null,"abstract":"Spectral regrowth of a CDMA signal and in-channel distortion causing the gain compression or expansion are analyzed using the power series and statistical theory. The proposed time-domain model of the CDMA signal is shown to give more accurate distortion estimates than the widely used narrow-band Gaussian noise assumption. The model was also used to show the difference between statistical properties of the CDMA signal and the Gaussian noise.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122104573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A SOI-BiCMOS 800 Mbps write driver for hard disk drives 用于硬盘驱动器的SOI-BiCMOS 800mbps写入驱动程序
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929820
N. Fujii, M. Kuraishi, T. Mochizuki, S. Irikuraz, T. Hirose
{"title":"A SOI-BiCMOS 800 Mbps write driver for hard disk drives","authors":"N. Fujii, M. Kuraishi, T. Mochizuki, S. Irikuraz, T. Hirose","doi":"10.1109/CICC.2001.929820","DOIUrl":"https://doi.org/10.1109/CICC.2001.929820","url":null,"abstract":"A current-driver write driver for a +5/-5 V preamplifier is described in this paper. This IC, which incorporates RC load for harmonic oscillation to enlarge the voltage swing across the head and Super Push-Pull Logic (SPL), drives the write driver with a good rise/fall time. This write driver, built with a 0.35 /spl mu/m SOI-BiCMOS process, has demonstrated a rise-time as short as 0.45 ns with a 160 mA peak-to-peak output write current.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129564872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Clock generator using factorial DLL for video applications 时钟生成器使用阶乘DLL用于视频应用程序
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929826
J. Bégueret, Y. Deval, O. Mazouffre, A. Spataro, P. Fouillat, E. Benoit, J. Mendoza
{"title":"Clock generator using factorial DLL for video applications","authors":"J. Bégueret, Y. Deval, O. Mazouffre, A. Spataro, P. Fouillat, E. Benoit, J. Mendoza","doi":"10.1109/CICC.2001.929826","DOIUrl":"https://doi.org/10.1109/CICC.2001.929826","url":null,"abstract":"This paper presents a clock generator dedicated to front-end processors for LCD and plasma monitor video applications. The topology is based on a factorial DLL, which can support all kind of standards (from VGA up to SXGA). Fabricated in a 2.5 V, 0.25 /spl mu/m, 6-metal CMOS VLSI process from STMicroelectronics, the maximum r.m.s. measured jitter is 17 ps. The power consumption is 17 mW at 200 MHz output frequency. The low cost area (0.08 mm/sup 2/) and the fully integrated structure make it well suited for such a video market.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127153285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A platform-based highly parallel digital signal processor 一种基于平台的高度并行数字信号处理器
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929787
T. Richter, W. Drescher, F. Engel, S. Kobayashi, V. Nikolajevic, Matthias Weiss, G. Fettweis
{"title":"A platform-based highly parallel digital signal processor","authors":"T. Richter, W. Drescher, F. Engel, S. Kobayashi, V. Nikolajevic, Matthias Weiss, G. Fettweis","doi":"10.1109/CICC.2001.929787","DOIUrl":"https://doi.org/10.1109/CICC.2001.929787","url":null,"abstract":"Realizations of demanding applications particularly in the field of mobile communications often require processing performance which is far beyond what is delivered by DSPs today. To avoid designing inflexible ASIC solutions a powerful, highly parallel DSP core for System-on-Chip domains is presented in this paper. Targeted for a wireless OFDM based modem application the fixed-point DSP core consists of 16/spl times/16-bit datapath units in parallel providing 640 M MAC operations per second. In a Galois field split mode 32 8-bit datapaths deliver 1.28 G MAC/s. The DSP is based on a scalable architecture which supports customization depending on the application needs. The 289 mm/sup 2/ chip was manufactured in a 0.35 /spl mu/m CMOS technology, operates at 40 MHz and dissipates <1 W from a 3.3 V supply. This low power approach outperforms commercial DSPs running at 200 MHz.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130550510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A system-on-chip for pressure-sensitive fabric 用于压敏织物的片上系统
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929812
M. Sergio, N. Manaresi, M. Tartagni, R. Canegallo, R. Guerrieri
{"title":"A system-on-chip for pressure-sensitive fabric","authors":"M. Sergio, N. Manaresi, M. Tartagni, R. Canegallo, R. Guerrieri","doi":"10.1109/CICC.2001.929812","DOIUrl":"https://doi.org/10.1109/CICC.2001.929812","url":null,"abstract":"This paper presents a mixed-signal system-on-chip (SOC) for decoding the pressure exerted over a large piece of smart fabric. The image map of the pressure applied over the fabric surface is achieved by detecting the capacitance variation between rows and columns of conductive fibers patterned on the two opposite sides of an elastic layer, like synthetic foam. The SOC approach allows one to reduce design time maintaining the flexibility to accommodate for different sensor sizes and to perform some image enhancement such as fixed pattern noise compensation and gamma correction. The chip has been designed in a 0.35 /spl mu/m 5 ML CMOS process to work at 40 MHz, 3.3 V power supply, in a fully reconfigurable arrangement of 128 rows and columns. The core area is 32 mm/sup 2/.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125494279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A hardware/software solution for embeddable FPGA 嵌入式FPGA的硬件/软件解决方案
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929726
F. Lien, J. Feng, E. Huang, C. Sun, Tao Liu, N. Liao, D. Hightower
{"title":"A hardware/software solution for embeddable FPGA","authors":"F. Lien, J. Feng, E. Huang, C. Sun, Tao Liu, N. Liao, D. Hightower","doi":"10.1109/CICC.2001.929726","DOIUrl":"https://doi.org/10.1109/CICC.2001.929726","url":null,"abstract":"This paper describes a novel FPGA architecture and related design software for embedding FPGA logic into ASIC designs. The requirements for embedding FPGAs include: fixed pinouts, predictable utilization, predictable and reasonable signal delays, scalability, die size control, and ease of layout. This paper describes Actel's embedded FPGA solution, VariCore/sup TM/.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126758704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design for manufacturability characterization and optimization of mixed-signal IP 混合信号IP的可制造性表征与优化设计
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929771
P. McNamara, S. Saxena, C. Guardiani, H. Taguchi, Emiko Yoshida, Naoki Takahashi, Koji Miyamoto, K. Sugawara, Takeshi Matsunaga
{"title":"Design for manufacturability characterization and optimization of mixed-signal IP","authors":"P. McNamara, S. Saxena, C. Guardiani, H. Taguchi, Emiko Yoshida, Naoki Takahashi, Koji Miyamoto, K. Sugawara, Takeshi Matsunaga","doi":"10.1109/CICC.2001.929771","DOIUrl":"https://doi.org/10.1109/CICC.2001.929771","url":null,"abstract":"This paper presents results of applying a statistically based parametric yield modeling approach to quantify current manufacturing yield and potential yield improvement of mixed-signal blocks. This design for manufacturability methodology is used to statistically characterize and quantify parametric yield optimization of a 2-channel 9-bit DAC manufactured in a 0.4C /spl mu/m CMOS process. Parametric yield loss characterization and optimization are validated in silicon to be 15% and 4%, respectively.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126353437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 165 MS/s 8-bit CMOS A/D converter with background offset cancellation 具有背景偏移抵消的165 MS/s 8位CMOS A/D转换器
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929745
G. Feygin, K. Nagaraj, R. Chattopadhyay, R. Herrera, I. Papantonopoulos, D. A. Martin, P. Wu, S. Pavan
{"title":"A 165 MS/s 8-bit CMOS A/D converter with background offset cancellation","authors":"G. Feygin, K. Nagaraj, R. Chattopadhyay, R. Herrera, I. Papantonopoulos, D. A. Martin, P. Wu, S. Pavan","doi":"10.1109/CICC.2001.929745","DOIUrl":"https://doi.org/10.1109/CICC.2001.929745","url":null,"abstract":"A 8-bit A/D converter using an efficient architecture is described. An important feature of this is a background offset cancellation scheme. This A/D converter has been implemented in a 0.18 /spl mu/m digital CMOS technology. It operates at up to 165 MS/s with an SNDR of 43.5 dB, a DNL of 0.7 LSB and an INL of 1 LSB. It occupies an active area of 0.9 mm/sup 2/ and has a power dissipation of 140 mW.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116090766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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