Design for manufacturability characterization and optimization of mixed-signal IP

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI:10.1109/CICC.2001.929771

P. McNamara, S. Saxena, C. Guardiani, H. Taguchi, Emiko Yoshida, Naoki Takahashi, Koji Miyamoto, K. Sugawara, Takeshi Matsunaga

引用次数: 3

Abstract

This paper presents results of applying a statistically based parametric yield modeling approach to quantify current manufacturing yield and potential yield improvement of mixed-signal blocks. This design for manufacturability methodology is used to statistically characterize and quantify parametric yield optimization of a 2-channel 9-bit DAC manufactured in a 0.4C /spl mu/m CMOS process. Parametric yield loss characterization and optimization are validated in silicon to be 15% and 4%, respectively.

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混合信号IP的可制造性表征与优化设计

本文介绍了应用基于统计的参数良率建模方法量化混合信号块的当前制造良率和潜在良率改进的结果。该可制造性方法设计用于统计表征和量化在0.4C /spl mu/m CMOS工艺中制造的2通道9位DAC的参数良率优化。参数化产率损失表征和优化分别在硅中验证为15%和4%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)

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