M. Sergio, N. Manaresi, M. Tartagni, R. Canegallo, R. Guerrieri
{"title":"A system-on-chip for pressure-sensitive fabric","authors":"M. Sergio, N. Manaresi, M. Tartagni, R. Canegallo, R. Guerrieri","doi":"10.1109/CICC.2001.929812","DOIUrl":null,"url":null,"abstract":"This paper presents a mixed-signal system-on-chip (SOC) for decoding the pressure exerted over a large piece of smart fabric. The image map of the pressure applied over the fabric surface is achieved by detecting the capacitance variation between rows and columns of conductive fibers patterned on the two opposite sides of an elastic layer, like synthetic foam. The SOC approach allows one to reduce design time maintaining the flexibility to accommodate for different sensor sizes and to perform some image enhancement such as fixed pattern noise compensation and gamma correction. The chip has been designed in a 0.35 /spl mu/m 5 ML CMOS process to work at 40 MHz, 3.3 V power supply, in a fully reconfigurable arrangement of 128 rows and columns. The core area is 32 mm/sup 2/.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2001.929812","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents a mixed-signal system-on-chip (SOC) for decoding the pressure exerted over a large piece of smart fabric. The image map of the pressure applied over the fabric surface is achieved by detecting the capacitance variation between rows and columns of conductive fibers patterned on the two opposite sides of an elastic layer, like synthetic foam. The SOC approach allows one to reduce design time maintaining the flexibility to accommodate for different sensor sizes and to perform some image enhancement such as fixed pattern noise compensation and gamma correction. The chip has been designed in a 0.35 /spl mu/m 5 ML CMOS process to work at 40 MHz, 3.3 V power supply, in a fully reconfigurable arrangement of 128 rows and columns. The core area is 32 mm/sup 2/.