Satoshi Kumaki, H. Takata, Y. Ajioka, T. Ooishi, K. Ishihara, A. Hanami, Takaharu Tsuji, Tetsuya Watanabe, C. Morishima, T. Yoshizawa, Hidenori Sato, S. Hattori, A. Koshio, K. Tsukamoto, T. Matsumura
{"title":"A 99-mm/sup 2/, 0.7-W, single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mbit embedded DRAM for portable 422P@HL encoder system","authors":"Satoshi Kumaki, H. Takata, Y. Ajioka, T. Ooishi, K. Ishihara, A. Hanami, Takaharu Tsuji, Tetsuya Watanabe, C. Morishima, T. Yoshizawa, Hidenori Sato, S. Hattori, A. Koshio, K. Tsukamoto, T. Matsumura","doi":"10.1109/CICC.2001.929815","DOIUrl":null,"url":null,"abstract":"A scalable single-chip 422P@ML MPEG-2 video, audio, and system encoder LSI for portable 422P@HL system is described. The encoder LSI is implemented using 0.13 /spl mu/m embedded DRAM technology. It integrates 3-M logic gates and 64-Mbit DRAM in an area of 99-mm/sup 2/. The power consumption is suppressed to 0.7-Watts by adopting a low power DRAM core. It performs real-time 422P@ML video encoding, audio encoding, and system encoding with no external DRAM. Furthermore, the encoder LSI realizes a 422P@HL video encoder with multi-chip configuration, due to its scalable architecture. This results in a PC-card size 422P@HL encoder with lowest power consumption for portable HDTV codec system.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2001.929815","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 16
Abstract
A scalable single-chip 422P@ML MPEG-2 video, audio, and system encoder LSI for portable 422P@HL system is described. The encoder LSI is implemented using 0.13 /spl mu/m embedded DRAM technology. It integrates 3-M logic gates and 64-Mbit DRAM in an area of 99-mm/sup 2/. The power consumption is suppressed to 0.7-Watts by adopting a low power DRAM core. It performs real-time 422P@ML video encoding, audio encoding, and system encoding with no external DRAM. Furthermore, the encoder LSI realizes a 422P@HL video encoder with multi-chip configuration, due to its scalable architecture. This results in a PC-card size 422P@HL encoder with lowest power consumption for portable HDTV codec system.