R. Haga, T. Kaneko, A. Nakayama, S. Miyano, H. Takenaka, K. Numata, Hiroyuki Koinuma, T. Hojo, A. Sato, T. Kouchi, K. Mimoto, M. Tazawa, T. Ohkubo, T. Andou, T. Amano
{"title":"生成嵌入式DRAM宏的接口套接字设计方法","authors":"R. Haga, T. Kaneko, A. Nakayama, S. Miyano, H. Takenaka, K. Numata, Hiroyuki Koinuma, T. Hojo, A. Sato, T. Kouchi, K. Mimoto, M. Tazawa, T. Ohkubo, T. Andou, T. Amano","doi":"10.1109/CICC.2001.929837","DOIUrl":null,"url":null,"abstract":"A new design methodology for embedded DRAM is introduced. The DRAM macro consists of common DRAM core and interface socket. Splitting the DRAM macro into common DRAM core and interface socket widens the reconfigurability of the functions of the macro. An experimental chip consists of 12M-bit DRAM core and synchronous interface socket was developed with 0.18 /spl mu/m technology.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Interface socket design methodology to generate embedded DRAM macros\",\"authors\":\"R. Haga, T. Kaneko, A. Nakayama, S. Miyano, H. Takenaka, K. Numata, Hiroyuki Koinuma, T. Hojo, A. Sato, T. Kouchi, K. Mimoto, M. Tazawa, T. Ohkubo, T. Andou, T. Amano\",\"doi\":\"10.1109/CICC.2001.929837\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new design methodology for embedded DRAM is introduced. The DRAM macro consists of common DRAM core and interface socket. Splitting the DRAM macro into common DRAM core and interface socket widens the reconfigurability of the functions of the macro. An experimental chip consists of 12M-bit DRAM core and synchronous interface socket was developed with 0.18 /spl mu/m technology.\",\"PeriodicalId\":101717,\"journal\":{\"name\":\"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-05-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2001.929837\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2001.929837","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Interface socket design methodology to generate embedded DRAM macros
A new design methodology for embedded DRAM is introduced. The DRAM macro consists of common DRAM core and interface socket. Splitting the DRAM macro into common DRAM core and interface socket widens the reconfigurability of the functions of the macro. An experimental chip consists of 12M-bit DRAM core and synchronous interface socket was developed with 0.18 /spl mu/m technology.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
