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Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)最新文献

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R(f)L(f)C coupled noise evaluation of an S/390 microprocessor chip S/390微处理器芯片的R(f)L(f)C耦合噪声评价
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929763
H.H. Smith, Aline Deutsch, S. Mehrotra, D. Widiger, M. Bowen, A. Dansky, G. Kopcsay, B. Krauter
{"title":"R(f)L(f)C coupled noise evaluation of an S/390 microprocessor chip","authors":"H.H. Smith, Aline Deutsch, S. Mehrotra, D. Widiger, M. Bowen, A. Dansky, G. Kopcsay, B. Krauter","doi":"10.1109/CICC.2001.929763","DOIUrl":"https://doi.org/10.1109/CICC.2001.929763","url":null,"abstract":"A coupling noise evaluation of a high performance S/390 microprocessor using a full chip RLC extraction and simulation process is presented. Review of on-chip wiring guidelines with respect to the inaccuracies of an RC coupling evaluation for known net topologies is discussed in terms of tool requirements for full-chip noise evaluation which include inductive coupling effects. The extraction and simulation approach is described in terms of algorithms and procedures used to account for the frequency dependent RLC effects in a manner that allow a full chip noise evaluation. Results are presented which compare noise amplitude differences between RC and R(f)L(f)C evaluations for the wiring data of an S/390 microprocessor as well as pertinent statistics such as run times and memory usage.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"299 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122423073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A new analytical model for high frequency MOSFET noise 一种新的高频MOSFET噪声分析模型
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929807
S. Guerrieri, F. Bonani, G. Ghione, M. A. Alam
{"title":"A new analytical model for high frequency MOSFET noise","authors":"S. Guerrieri, F. Bonani, G. Ghione, M. A. Alam","doi":"10.1109/CICC.2001.929807","DOIUrl":"https://doi.org/10.1109/CICC.2001.929807","url":null,"abstract":"A new analytical approach to extract high frequency MOSFET noise is presented and its validation is carried out with careful comparison with numerical physics-based 2D noise simulations. The analytical formulation accounts for drain and gate noise spectra and their correlation, and extends the classical van der Ziel approach to short channel devices. The field dependency of the diffusivity is shown to affect the noise performances significantly in short-gate devices. The new model is well suited to be exploited in circuit simulation in conjunction with compact models such as BSIMA.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127611142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Demonstration of a switched resonator concept in a dual-band monolithic CMOS LC-tuned VCO 双带单片CMOS lc调谐压控振荡器中开关谐振器概念的演示
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929756
Seong-Mo Yim, K. O. Kenneth
{"title":"Demonstration of a switched resonator concept in a dual-band monolithic CMOS LC-tuned VCO","authors":"Seong-Mo Yim, K. O. Kenneth","doi":"10.1109/CICC.2001.929756","DOIUrl":"https://doi.org/10.1109/CICC.2001.929756","url":null,"abstract":"A switched resonator concept which allows better trade-off between phase noise and power consumption is demonstrated using a dual band VCO. The dual-band VCO operates near 900 MHz and 1.8 GHz with phase noise of -125 and 123 dBc/Hz at a 600-KHz offset and 16-mW power consumption. Compared to a single band 1.8 GHz VCO, the dual-band VCO has almost the same phase noise and power consumption.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133047043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 121
Dedicated system-level simulation of /spl Delta//spl Sigma/ modulators 专用系统级模拟/spl Delta//spl Sigma/调制器
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929799
K. Francken, M. Vogels, G. Gielen
{"title":"Dedicated system-level simulation of /spl Delta//spl Sigma/ modulators","authors":"K. Francken, M. Vogels, G. Gielen","doi":"10.1109/CICC.2001.929799","DOIUrl":"https://doi.org/10.1109/CICC.2001.929799","url":null,"abstract":"A new approach is presented for significantly speeding up system-level simulation of /spl Delta//spl Sigma/ modulators. The method is based on high-level simulation that can be combined with an acceleration algorithm and has been implemented in C. Also, the decimator has been included yielding a complete and fast simulation of the whole converter. This reduces the bottleneck seen in system-level simulation of complete systems, e.g. receiver front-ends. Different topologies are included as well as the effects of most important nonidealities. Experimental results show the effectiveness of the approach.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123420679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A one chip super graphics CPU with direct unified memory controller suitable for car information and control system 一种适合于汽车信息与控制系统的带有直接统一存储控制器的单片超级图形CPU
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929814
Y. Nakatsuka, Tetsuya Shhomura, Y. Morita, Kazuhisa Takami, Manabu Joh, Masahisa Narita, Kazushige Yamagishi, Yutaka Okada, Jun Satoh
{"title":"A one chip super graphics CPU with direct unified memory controller suitable for car information and control system","authors":"Y. Nakatsuka, Tetsuya Shhomura, Y. Morita, Kazuhisa Takami, Manabu Joh, Masahisa Narita, Kazushige Yamagishi, Yutaka Okada, Jun Satoh","doi":"10.1109/CICC.2001.929814","DOIUrl":"https://doi.org/10.1109/CICC.2001.929814","url":null,"abstract":"A one chip super graphics CPU with graphics and unified memory controller has been developed. It requires no dedicated graphics memory and has significantly lower system cost with 1.6 times higher performance than CPUs with state-of-the-art technology. Its process and package are 0.18 /spl mu/m and 256 pin QFP, respectively.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123849118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 2.7 V CMOS GSM/WCDMA continuous-time filter with automatic tuning 具有自动调谐功能的2.7 V CMOS GSM/WCDMA连续时间滤波器
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929713
S. Lindfors, Tuomas Hollman, T. Salo, K. Halonen
{"title":"A 2.7 V CMOS GSM/WCDMA continuous-time filter with automatic tuning","authors":"S. Lindfors, Tuomas Hollman, T. Salo, K. Halonen","doi":"10.1109/CICC.2001.929713","DOIUrl":"https://doi.org/10.1109/CICC.2001.929713","url":null,"abstract":"A 5th-order continuous-time baseband filter with 7-step gain control for a dual-mode cellular phone was implemented. A cascade of a real pole and a ladder filter implementing the complex pole pairs was used for low noise. The GBW of the opamps was made programmable to reduce the power consumption in the GSM-mode. The corner frequency tuning was facilitated by integrating a 1-bit DAC with the filter and a digital tuning circuit separately with an ADC. The integrated input referred noise is 6.9 /spl mu/V and 13.6 /spl mu/V and the circuit consumes 13 mW and 21.8 mW in the GSM- and WCDMA-modes, respectively. The IIP3 is +25 dBV in the WCDMA-mode.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126225620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 220 mW 1 Gb/s 1024-bit rate-1/2 low density parity check code decoder 220mw 1gb /s 1024比特率1/2低密度奇偶校验码解码器
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929780
A. Blanksby, C. Howland
{"title":"A 220 mW 1 Gb/s 1024-bit rate-1/2 low density parity check code decoder","authors":"A. Blanksby, C. Howland","doi":"10.1109/CICC.2001.929780","DOIUrl":"https://doi.org/10.1109/CICC.2001.929780","url":null,"abstract":"A 1024 bit rate-1/2 Low Density Parity Check (LDPC) code decoder has been implemented that matches the coding gain of equivalent turbo codes. The parallel decoder architecture supports throughputs up to 1 Gb/s and convergence in the decoding algorithm translates into extremely low switching activity with power dissipation under 220 mW.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130242104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 588
A 2 GB/s high speed link with differential simultaneous bi-directional IO 2 GB/s高速链路，差分同步双向IO
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929831
D. R. Cecchi, Charles C. Hanson, C. W. Preuss
{"title":"A 2 GB/s high speed link with differential simultaneous bi-directional IO","authors":"D. R. Cecchi, Charles C. Hanson, C. W. Preuss","doi":"10.1109/CICC.2001.929831","DOIUrl":"https://doi.org/10.1109/CICC.2001.929831","url":null,"abstract":"The data bandwidth of an existing 1 GB/s high speed link is increased to 2 GB/s by use of differential simultaneous bi-directional signaling. This signaling technique allows a physical channel to carry two independent data streams, effectively doubling the data rate per IO. The driver also provides digital precompensation to counteract intersymbol interference due to skin effect attenuation.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121996264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 900 MHz, 0.9 V low-power CMOS downconversion mixer 900mhz, 0.9 V低功耗CMOS下变频混频器
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929835
C. J. Debono, F. Maloberti, J. Micaller
{"title":"A 900 MHz, 0.9 V low-power CMOS downconversion mixer","authors":"C. J. Debono, F. Maloberti, J. Micaller","doi":"10.1109/CICC.2001.929835","DOIUrl":"https://doi.org/10.1109/CICC.2001.929835","url":null,"abstract":"A low-voltage, low-power mixer operating at a supply voltage of 0.9 V while consuming 4.7 mW is presented. The circuit achieves the multiplication using current mode processing. Moreover, non-conventional differential pairs that do not require current tail generators are utilized. The circuit has been fabricated in a standard double-poly, triple-metal 0.35 /spl mu/m CMOS process having a threshold voltage of 0.6 V. Measurement results for 900 MHz and 800 MHz input signals indicate that the circuit has an IIP3 of 3.5 dBm, a 1 dB compression point of -8 dBm and a noise figure of 13.5 dB.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125928823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
A single chip terminal solution for high-end telephone applications 用于高端电话应用的单芯片终端解决方案
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929813
Vinod Nair Gopikuttan Nair, M. Erdmann, S. M. Mishra, J. Povazanec, A. Shaligram, C. Hu
{"title":"A single chip terminal solution for high-end telephone applications","authors":"Vinod Nair Gopikuttan Nair, M. Erdmann, S. M. Mishra, J. Povazanec, A. Shaligram, C. Hu","doi":"10.1109/CICC.2001.929813","DOIUrl":"https://doi.org/10.1109/CICC.2001.929813","url":null,"abstract":"The single chip telephone IC, INCA (INfineon Codec with U/sub PN/ transceiver and embedded microcontroller featuring Acoustic echo cancellation), integrates all the functions necessary for a digital voice and data terminal. With the 2-wire U/sub PN/ analog line transceiver, the INCA implements all subscriber access functions for digital terminals. Key feature of the chip is a smart acoustic echo cancellation and suppression algorithm, which allows comfortable full-duplex speakerphone conversations. Different digital interfaces allow connection to a variety of devices, including a 12 Mb/s USB (Universal Serial Bus) interface for PC host communication. The basic application of the INCA is in terminal equipment, where microphone, loudspeaker, headset and handset can be connected directly to the analog front end. Additionally the INCA provides a mechanism to control other U/sub PN/ terminals. This mode allows one to cascade U/sub PN/ telephones via its IOM-2 (ISDN Oriented Modular) interface. The INCA is a 0.35 /spl mu/ CMOS device and operates with a single 3.3 V supply.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125119379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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