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Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)最新文献

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An ASIC-embedded content addressable memory with power-saving and design for test features 一种嵌入式asic内容可寻址存储器，具有节电和测试功能设计
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929751
T. Chadwick, T. Gordon, R. Nadkarni, Jeremy Rowland
{"title":"An ASIC-embedded content addressable memory with power-saving and design for test features","authors":"T. Chadwick, T. Gordon, R. Nadkarni, Jeremy Rowland","doi":"10.1109/CICC.2001.929751","DOIUrl":"https://doi.org/10.1109/CICC.2001.929751","url":null,"abstract":"As the available circuit counts of standard-cell ASICs continue to increase, the issues of power dissipation and testability become increasingly important. In response to this trend, the embedded content addressable memory (CAM) described herein was designed with an emphasis on reducing active power dissipation and on improving the in-system testability via built-in self-test (BIST). At the same time, the CAM macro has been designed with flexibility in mind. Application examples will highlight this aspect of the macro. This CAM has been designed and manufactured in a 0.18 /spl mu/m photolithography process with copper metallization. Results of hardware observations from a test chip confirm functionality in silicon.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117352633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Design techniques for very low power ADCs 超低功耗adc的设计技术
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929742
R. Taft, M. R. Tursi, Andrew Glenny
{"title":"Design techniques for very low power ADCs","authors":"R. Taft, M. R. Tursi, Andrew Glenny","doi":"10.1109/CICC.2001.929742","DOIUrl":"https://doi.org/10.1109/CICC.2001.929742","url":null,"abstract":"The three low-power ADC techniques of interleaving-by-4 with an amplifier reset and master sampling clock, using self-regulating CMOS push-pull amplifiers, and a hybrid comparator are described. They are demonstrated in an 8-bit 100 MSPS ADC which achieves +/- 0.25 LSB DNL and 7.5 effective bits with very low power, 54 mW at 2.7 V supply. The same 8-bit ADC, if optimized for 200 MSPS operation at 2.7 V, obtains a DNL below 0.4 LSB, and 7.3 (7.1) effective bits for a 10 MHz (100 MHz) input while consuming just 182 mW.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132382989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A design environment for high throughput, low power dedicated signal processing systems 高吞吐量，低功耗专用信号处理系统的设计环境
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929839
W. R. Davis, Ning Zhang, K. Camera, F. Chen, D. Markovic, N. Chan, B. Nikolić, R. Brodersen
{"title":"A design environment for high throughput, low power dedicated signal processing systems","authors":"W. R. Davis, Ning Zhang, K. Camera, F. Chen, D. Markovic, N. Chan, B. Nikolić, R. Brodersen","doi":"10.1109/CICC.2001.929839","DOIUrl":"https://doi.org/10.1109/CICC.2001.929839","url":null,"abstract":"A hierarchical automated design flow for low-energy direct-mapped signal processing integrated circuits is presented. A modular framework based on a combined Simulink and floorplan description drives automatic layout generation. Automatic characterization of layout improves system-level estimates. The flow is demonstrated on the subsystems of CDMA and OFDM receivers and a 300 k transistor test-chip.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"490 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126809418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 121
An anti-blocker structure MOSFET-C filter for a direct conversion receiver 用于直接转换接收机的抗阻塞结构MOSFET-C滤波器
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929712
A. Yoshizawa, Y. Tsividis
{"title":"An anti-blocker structure MOSFET-C filter for a direct conversion receiver","authors":"A. Yoshizawa, Y. Tsividis","doi":"10.1109/CICC.2001.929712","DOIUrl":"https://doi.org/10.1109/CICC.2001.929712","url":null,"abstract":"A linearized MOSFET-C lowpass filter suitable for a baseband channel selection filter for a direct conversion receiver is presented. Using polysilicon resistors instead of MOSFET resistors in the input and output part, the filter achieves very high out-of-band linearity but keeps the original transfer function of the filter under a continuous on-chip cutoff tuning scheme. The filter achieves -1.8 dBV in-band IIP3, +27.8 dBV out-of-band IIP3, +93.8 dBV out-of-band IIP2 and 46.7 /spl mu/Vrms input-referred noise.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125888859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
FeRAM device and circuit technologies fully compatible with advanced CMOS FeRAM器件和电路技术与先进的CMOS完全兼容
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929749
H. Toyoshima, S. Kobayashi, J. Yamada, T. Miwa, H. Koike, H. Takeuchi, H. Mori, N. Kasai, Y. Maejima, N. Tanabe, T. Tatsumi, H. Hada
{"title":"FeRAM device and circuit technologies fully compatible with advanced CMOS","authors":"H. Toyoshima, S. Kobayashi, J. Yamada, T. Miwa, H. Koike, H. Takeuchi, H. Mori, N. Kasai, Y. Maejima, N. Tanabe, T. Tatsumi, H. Hada","doi":"10.1109/CICC.2001.929749","DOIUrl":"https://doi.org/10.1109/CICC.2001.929749","url":null,"abstract":"Recent progress in FeRAM device and circuit technologies that are fully compatible with advanced CMOS logic is described. We have developed a ferroelectric capacitor of a CMVP (capacitor-on-Metal/Via-stacked-Plug) memory cell that is fabricated after the completion of multilevel metallization. A 0.35-/spl mu/m 2T/2C FeRAM macro based on CMVP has been fabricated for smart card applications. The chip features a wide operation voltage range, high write/read endurance, low consumption current, and a flexible memory size. The CMVP technologies also enable a 0.25-/spl mu/m ASIC SRAM macro to be nonvolatile (NV-SRAM: nonvolatile SRAM). The memory cell consists of a six-transistor SRAM cell and two stacked back-up ferroelectric capacitors. A Vdd/2 plate line architecture makes read/write fatigue virtually negligible.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125235662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A low-power CMOS 155 Mb/s transceiver for SONET/SDH over co-ax and fibre 低功耗CMOS 155mb /s收发器，用于同轴和光纤上的SONET/SDH
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929739
M. Altmann, J. Caia, R. Morle, Michael Dunsmore, Y. Xie, N. Kocaman
{"title":"A low-power CMOS 155 Mb/s transceiver for SONET/SDH over co-ax and fibre","authors":"M. Altmann, J. Caia, R. Morle, Michael Dunsmore, Y. Xie, N. Kocaman","doi":"10.1109/CICC.2001.929739","DOIUrl":"https://doi.org/10.1109/CICC.2001.929739","url":null,"abstract":"This paper describes a single-chip mixed-signal 155 Mb/s all-CMOS SONET/SDH transceiver for operation over both co-ax and fibre links. The copper interface includes input common mode control, a digitally-controlled adaptive analog AGC and equalizer, a pulse-shaping filter with a tracking PLL, and PLL-based timing recovery with digital timing offset cancellation. Digital post-processing includes a CMI decoder and code violation detector, LOS detection, and SONET/SDH frame detection with byte relation. The device was fabricated in a digital 0.35 /spl mu/m CMOS process. The 3.3 V device consumes 150 mA to 210 mA including I/O. Recovered clock jitter is <20 ps/sub RMS/. The equalizer operates error-free up to 180 m of RG59-U cable.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123481826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A comparison of CMOS and SiGe LNA's and mixers for wireless LAN application 无线局域网应用中CMOS和SiGe LNA及混频器的比较
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929836
Xi Li, T. Brogan, Mark Esposito, B. Myers, K. O. Kenneth
{"title":"A comparison of CMOS and SiGe LNA's and mixers for wireless LAN application","authors":"Xi Li, T. Brogan, Mark Esposito, B. Myers, K. O. Kenneth","doi":"10.1109/CICC.2001.929836","DOIUrl":"https://doi.org/10.1109/CICC.2001.929836","url":null,"abstract":"2.4-GHz CMOS LNA and mixer for a high performance wireless LAN chipset fabricated in a 0.25-/spl mu/m foundry digital CMOS process were compared to the SiGe bipolar circuits using the same topology and almost identical schematic. The CMOS circuits were housed in the same package with the same pinout, and tested on the same PC board under similar bias conditions as those for the SiGe bipolar circuits. The CMOS LNA and mixer can match the SiGe performance with a 15 to 20% increase in power consumption, and a direct migration from bipolar to CMOS can be realized without major changes in circuits and systems.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129554079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
An IF CMOS signal component separator chip for LINC transmitters 用于LINC变送器的中频CMOS信号元件分离芯片
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929721
B. Shi, Lars Sundström
{"title":"An IF CMOS signal component separator chip for LINC transmitters","authors":"B. Shi, Lars Sundström","doi":"10.1109/CICC.2001.929721","DOIUrl":"https://doi.org/10.1109/CICC.2001.929721","url":null,"abstract":"The LINC transmitter provides linear amplification using highly nonlinear but power efficient amplifiers. The signal component separator (SCS) is a crucial function of LINC. This paper presents an IF SCS chip implemented in a 0.35 /spl mu/m CMOS process using a design based on voltage-translinear circuits. The experimental LINC transmitter, built with the chip and nonlinear amplifiers, had output spurious levels some -55 dBc and -48 dBc for a NADC signal and an IS-95 signal, respectively. This implies a high degree of linearity.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129563047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A deterministic scan-BIST architecture with application to field testing of high-availability systems 一种用于高可用性系统现场测试的确定性扫描- bist体系结构
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929768
S. Swaminathan, K. Chakrabarty
{"title":"A deterministic scan-BIST architecture with application to field testing of high-availability systems","authors":"S. Swaminathan, K. Chakrabarty","doi":"10.1109/CICC.2001.929768","DOIUrl":"https://doi.org/10.1109/CICC.2001.929768","url":null,"abstract":"We propose an autonomous, deterministic scan-BIST architecture that allows compact, precomputed test sets with complete fault coverage to be used for field testing. The use of such short test sequences is desirable in safety-critical systems since it reduces the error latency. It also reduces testing time and therefore allows periodic field testing to be carried out with low system downtime. We synthesize the BIST logic for several ISCAS 89 benchmarks and industrial circuit modules and show that the BIST overhead is low in all cases. The proposed design can also be efficiently used with a mixed-mode BIST strategy.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133183257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
RTL morphing: making IP-reuse work in system-on-a-chip designs RTL变形:使ip复用在片上系统设计中工作
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929840
S. Yamashita, H. Chikata, Y. Onishi, Naoki Kato, Tomomi Hiyama, K. Yano
{"title":"RTL morphing: making IP-reuse work in system-on-a-chip designs","authors":"S. Yamashita, H. Chikata, Y. Onishi, Naoki Kato, Tomomi Hiyama, K. Yano","doi":"10.1109/CICC.2001.929840","DOIUrl":"https://doi.org/10.1109/CICC.2001.929840","url":null,"abstract":"The proposed RTL morphing enables true IP-reuse design through flexible control of the RTL structure under the changes in performance requirements or delay constraints. This flexible RTL restructuring is provided by a new path-depth controlling method, which can optimize the depth of any path by changing the if-then-else nesting order of a basic logic unit (called a decision unit). The use of RTL morphing reduces the design period of a time-to-market pressured SoC of 4M transistors by two months with 18% operating frequency improvement.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114223425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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