FeRAM器件和电路技术与先进的CMOS完全兼容

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI:10.1109/CICC.2001.929749

H. Toyoshima, S. Kobayashi, J. Yamada, T. Miwa, H. Koike, H. Takeuchi, H. Mori, N. Kasai, Y. Maejima, N. Tanabe, T. Tatsumi, H. Hada

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引用次数: 5

摘要

描述了与先进CMOS逻辑完全兼容的FeRAM器件和电路技术的最新进展。我们开发了一种在多层金属化完成后制造的CMVP(电容器-on- metal / via - stacking - plug)存储电池的铁电电容器。制作了一个基于CMVP的0.35-/spl mu/m 2T/2C FeRAM宏，用于智能卡应用。该芯片具有宽工作电压范围、高写入/读取耐久性、低功耗电流和灵活的内存大小。CMVP技术还使0.25-/spl mu/m的ASIC SRAM宏是非易失性的(NV-SRAM:非易失性SRAM)。存储单元由一个六晶体管SRAM单元和两个堆叠备用铁电电容器组成。Vdd/2板线架构使读/写疲劳几乎可以忽略不计。

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FeRAM device and circuit technologies fully compatible with advanced CMOS

Recent progress in FeRAM device and circuit technologies that are fully compatible with advanced CMOS logic is described. We have developed a ferroelectric capacitor of a CMVP (capacitor-on-Metal/Via-stacked-Plug) memory cell that is fabricated after the completion of multilevel metallization. A 0.35-/spl mu/m 2T/2C FeRAM macro based on CMVP has been fabricated for smart card applications. The chip features a wide operation voltage range, high write/read endurance, low consumption current, and a flexible memory size. The CMVP technologies also enable a 0.25-/spl mu/m ASIC SRAM macro to be nonvolatile (NV-SRAM: nonvolatile SRAM). The memory cell consists of a six-transistor SRAM cell and two stacked back-up ferroelectric capacitors. A Vdd/2 plate line architecture makes read/write fatigue virtually negligible.

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Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)

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