An ASIC-embedded content addressable memory with power-saving and design for test features

Abstract

As the available circuit counts of standard-cell ASICs continue to increase, the issues of power dissipation and testability become increasingly important. In response to this trend, the embedded content addressable memory (CAM) described herein was designed with an emphasis on reducing active power dissipation and on improving the in-system testability via built-in self-test (BIST). At the same time, the CAM macro has been designed with flexibility in mind. Application examples will highlight this aspect of the macro. This CAM has been designed and manufactured in a 0.18 /spl mu/m photolithography process with copper metallization. Results of hardware observations from a test chip confirm functionality in silicon.