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Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)最新文献

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A 10 GHz SiGe BiCMOS phase-locked-loop frequency synthesizer 10 GHz SiGe BiCMOS锁相环频率合成器
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929843
B. Klepser, M. Scholz, E. Götz
{"title":"A 10 GHz SiGe BiCMOS phase-locked-loop frequency synthesizer","authors":"B. Klepser, M. Scholz, E. Götz","doi":"10.1109/CICC.2001.929843","DOIUrl":"https://doi.org/10.1109/CICC.2001.929843","url":null,"abstract":"A SiGe BiCMOS phase-lock-loop circuit is presented. A maximum operational frequency of 10 GHz and a current consumption of 7.6 mA, i.e. 17 mW is demonstrated. For a 9 mW low power version, a maximum frequency of 4.7 GHz is determined. This demonstrates the speed and power advantage of the SiGe BiCMOS technology for wireless communications.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122211675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
DSP techniques for optical transceivers 光收发器的DSP技术
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929775
K. Azadet, E. Haratsch, H. Kim, F. Saibi, J. Saunders, M. Shaffer, L. Song, Meng-Lin Yu
{"title":"DSP techniques for optical transceivers","authors":"K. Azadet, E. Haratsch, H. Kim, F. Saibi, J. Saunders, M. Shaffer, L. Song, Meng-Lin Yu","doi":"10.1109/CICC.2001.929775","DOIUrl":"https://doi.org/10.1109/CICC.2001.929775","url":null,"abstract":"In this tutorial paper, we present the application of well-known DSP techniques used in lower speed wireline and wireless applications, to high-speed optical communications. After an introduction on today's optical network architecture and typical optical channel impairments, we study techniques such as fiber equalization, maximum likelihood detection, and forward error correction, with special emphasis on VLSI implementation.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123447547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Design of high-speed circuits for optical communication systems 光通信系统高速电路的设计
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929789
Behzad Razavi
{"title":"Design of high-speed circuits for optical communication systems","authors":"Behzad Razavi","doi":"10.1109/CICC.2001.929789","DOIUrl":"https://doi.org/10.1109/CICC.2001.929789","url":null,"abstract":"This paper presents the design of circuits and architectures for optical communication transceivers. First, a system overview illustrating the challenges in high-speed implementations is given. Next, the design of transimpedance amplifiers and limiters is discussed and the problem of clock and data recovery is addressed. Finally, jitter issues and methods of estimating the jitter are introduced.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122873470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Comparative low frequency noise analysis of bipolar and MOS transistors using an advanced complementary BiCMOS technology 采用先进的互补BiCMOS技术对双极和MOS晶体管进行低频噪声比较分析
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929806
J. Babcock, Bill Loftin, Praful Madhani, Xinfen Chen, A. Pinto, D. Schroder
{"title":"Comparative low frequency noise analysis of bipolar and MOS transistors using an advanced complementary BiCMOS technology","authors":"J. Babcock, Bill Loftin, Praful Madhani, Xinfen Chen, A. Pinto, D. Schroder","doi":"10.1109/CICC.2001.929806","DOIUrl":"https://doi.org/10.1109/CICC.2001.929806","url":null,"abstract":"In this paper, for the first time we compare 1/f noise in both complementary bipolar and complementary MOSFET transistors fabricated on thick film bonded SOI with full dielectric isolation capability. For MOS devices, a new relationship for 1/f noise is given which allows intuitive insight when comparing technologies. Both bipolar and MOS transistors show agreement to a number fluctuation model for noise mechanisms. A factor of 2 lower 1/f noise is determined for the PNP in comparison to NPN transistors. For this technology generation, bipolar transistors indicate an order of magnitude lower noise level when compared to MOSFETs under similar drive currents and effective area conditions. Finally, we discuss generation recombination noise, which can be observed in some of the devices.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116967551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
A 'digital' 6-bit ADC in 0.25 /spl mu/m CMOS 一个“数字”6位ADC在0.25 /spl μ m CMOS
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929743
Conor Donovan, M. Flynn
{"title":"A 'digital' 6-bit ADC in 0.25 /spl mu/m CMOS","authors":"Conor Donovan, M. Flynn","doi":"10.1109/CICC.2001.929743","DOIUrl":"https://doi.org/10.1109/CICC.2001.929743","url":null,"abstract":"Traditionally, circuit designers have adopted analog techniques to overcome comparator offset in flash converters. These schemes usually have an adverse effect on area and power consumption, and more seriously do not scale easily to low voltage processes. We describe a digital technique, which removes the accuracy constraints from the comparators. With no analog matching requirement, the comparators can be small, fast and power efficient. A 6-bit prototype converter built in a standard 0.25 /spl mu/m digital CMOS process occupies 1.2 mm/sup 2/ and dissipates 110 mW from a 2.2 V supply at 300 Ms/s.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124346516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Successful modular process technology for system-on-a-chip applications 芯片上系统应用的成功模块化工艺技术
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929811
W. Cochran
{"title":"Successful modular process technology for system-on-a-chip applications","authors":"W. Cochran","doi":"10.1109/CICC.2001.929811","DOIUrl":"https://doi.org/10.1109/CICC.2001.929811","url":null,"abstract":"By traditional standards, virtually all state-of-the-art technology offerings are, to some degree, modular. The role of various modular process technologies on systems-on-a-chip is explored. Keys to successful development of modular process technology are reviewed. Examples of modular process technology usage for the VLSI system chips are given, along with potential and actual issues encountered. Cost/benefit issues are examined and the future of modular process technology and system-on-a-chip design is explored.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133960148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Band-gap references for near 1-V operation in standard CMOS technology 标准CMOS技术中接近1 v操作的带隙参考
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929823
A. Pierazzi, A. Boni, C. Morandi
{"title":"Band-gap references for near 1-V operation in standard CMOS technology","authors":"A. Pierazzi, A. Boni, C. Morandi","doi":"10.1109/CICC.2001.929823","DOIUrl":"https://doi.org/10.1109/CICC.2001.929823","url":null,"abstract":"This paper presents two novel implementations of the current-mode band-gap reference (BGR) which support the very low supply voltages of the near future CMOS technologies, without resorting to special devices. Moreover, the problem of the start-up of low-voltage BGRs is discussed and a simple solution which guarantees correct start-up over process, supply voltage and temperature variations is proposed. The band-gap references were implemented in a conventional 0.35 /spl mu/m. CMOS technology and provides an output voltage of about 500 mV.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132212995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
An IF FSK demodulator for Bluetooth in 0.35 /spl mu/m CMOS 一种用于蓝牙的0.35 /spl mu/m CMOS中频FSK解调器
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929834
H. Darabi, S. Khorram, B. Ibrahim, M. Rofougaran, A. Rofougaran
{"title":"An IF FSK demodulator for Bluetooth in 0.35 /spl mu/m CMOS","authors":"H. Darabi, S. Khorram, B. Ibrahim, M. Rofougaran, A. Rofougaran","doi":"10.1109/CICC.2001.929834","DOIUrl":"https://doi.org/10.1109/CICC.2001.929834","url":null,"abstract":"An FSK demodulator intended for use in Bluetooth is implemented in a 0.35 /spl mu/m CMOS process. The entire demodulator, integrated as a part of a low-IF receiver with 2 MHz intermediate frequency, consumes 3 mA from 2.7 V supply. The required signal-to-noise ratio (SNR) for 0.1% bit error rate (BER) is about 18 dB.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123500590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
V/sub TH/-hopping scheme for 82% power saving in low-voltage processors V/sub - TH/跳频方案，可在低压处理器中节省82%的功耗
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929731
K. Nose, M. Hirabayashi, H. Kawaguchi, Seongsoo Lee, T. Sakurai
{"title":"V/sub TH/-hopping scheme for 82% power saving in low-voltage processors","authors":"K. Nose, M. Hirabayashi, H. Kawaguchi, Seongsoo Lee, T. Sakurai","doi":"10.1109/CICC.2001.929731","DOIUrl":"https://doi.org/10.1109/CICC.2001.929731","url":null,"abstract":"A threshold voltage hopping (V/sub TH/-hopping) scheme is proposed where V/sub TH/ is dynamically controlled through software depending on a workload. V/sub TH/-hopping is shown to reduce the power to 18% of the fixed low-V/sub TH/ circuits in 0.5 V supply voltage regime for multimedia applications. A positive back-gate bias scheme within V/sub TH/-hopping is presented for the high-performance and low-voltage processors. The measurement result shows about 90% leakage power reduction is possible by using V/sub TH/-hopping.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129604830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
C++ based system design of a 72 Mb/s OFDM transceiver for wireless LAN 基于c++的无线局域网72 Mb/s OFDM收发器系统设计
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929817
D. Verkest, W. Eberle, P. Schaumont, B. Gyselinckx, Serge Vemalde
{"title":"C++ based system design of a 72 Mb/s OFDM transceiver for wireless LAN","authors":"D. Verkest, W. Eberle, P. Schaumont, B. Gyselinckx, Serge Vemalde","doi":"10.1109/CICC.2001.929817","DOIUrl":"https://doi.org/10.1109/CICC.2001.929817","url":null,"abstract":"This paper describes the system-level design process followed for the implementation of a 72 Mb/s OFDM (Orthogonal Frequency Division Multiplexing) transceiver for 5 GHz wireless LAN (Local Area Network) that is realized in 0.18 /spl mu/m CMOS technology. The starting point is a high-level specification using the general-purpose programming language C++. By making use of a set of class libraries developed internally at IMEC, architectural trade-offs can be easily explored. The open nature of a C++ based design environment supports the re-use of previously designed building blocks and allows designers to extend the typically supported design-flow eliminating the need for manual generation and correction of synthesis and verification scripts. Automated HDL (Hardware Description Language) code generation from the C++ descriptions creates the link to standard synthesis tools and back-end flows.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126013160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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