A low-power CMOS 155 Mb/s transceiver for SONET/SDH over co-ax and fibre

Abstract

This paper describes a single-chip mixed-signal 155 Mb/s all-CMOS SONET/SDH transceiver for operation over both co-ax and fibre links. The copper interface includes input common mode control, a digitally-controlled adaptive analog AGC and equalizer, a pulse-shaping filter with a tracking PLL, and PLL-based timing recovery with digital timing offset cancellation. Digital post-processing includes a CMI decoder and code violation detector, LOS detection, and SONET/SDH frame detection with byte relation. The device was fabricated in a digital 0.35 /spl mu/m CMOS process. The 3.3 V device consumes 150 mA to 210 mA including I/O. Recovered clock jitter is <20 ps/sub RMS/. The equalizer operates error-free up to 180 m of RG59-U cable.