A 220 mW 1 Gb/s 1024-bit rate-1/2 low density parity check code decoder

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI:10.1109/CICC.2001.929780

A. Blanksby, C. Howland

引用次数: 588

Abstract

A 1024 bit rate-1/2 Low Density Parity Check (LDPC) code decoder has been implemented that matches the coding gain of equivalent turbo codes. The parallel decoder architecture supports throughputs up to 1 Gb/s and convergence in the decoding algorithm translates into extremely low switching activity with power dissipation under 220 mW.

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220mw 1gb /s 1024比特率1/2低密度奇偶校验码解码器

实现了与等效turbo码的编码增益相匹配的1024比特率-1/2低密度奇偶校验(LDPC)码解码器。并行解码器架构支持高达1gb /s的吞吐量，解码算法的收敛转化为极低的切换活动，功耗低于220 mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)

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