一个99毫米/sup 2/， 0.7 w，单片MPEG-2 422P@ML视频，音频和系统编码器与64兆嵌入式DRAM便携式422P@HL编码器系统

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI:10.1109/CICC.2001.929815

Satoshi Kumaki, H. Takata, Y. Ajioka, T. Ooishi, K. Ishihara, A. Hanami, Takaharu Tsuji, Tetsuya Watanabe, C. Morishima, T. Yoshizawa, Hidenori Sato, S. Hattori, A. Koshio, K. Tsukamoto, T. Matsumura

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引用次数: 16

摘要

描述了用于便携式422P@HL系统的可扩展单芯片422P@ML MPEG-2视频、音频和系统编码器LSI。编码器LSI采用0.13 /spl mu/m嵌入式DRAM技术实现。它集成了3-M逻辑门和64-Mbit DRAM，面积为99-mm/sup 2/。采用低功耗DRAM内核，功耗降至0.7瓦。它执行实时422P@ML视频编码、音频编码和系统编码，无需外部DRAM。此外，由于其可扩展的架构，该编码器LSI实现了具有多芯片配置的422P@HL视频编码器。这导致了pc卡大小422P@HL编码器与最低功耗的便携式HDTV编解码器系统。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 99-mm/sup 2/, 0.7-W, single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mbit embedded DRAM for portable 422P@HL encoder system

A scalable single-chip 422P@ML MPEG-2 video, audio, and system encoder LSI for portable 422P@HL system is described. The encoder LSI is implemented using 0.13 /spl mu/m embedded DRAM technology. It integrates 3-M logic gates and 64-Mbit DRAM in an area of 99-mm/sup 2/. The power consumption is suppressed to 0.7-Watts by adopting a low power DRAM core. It performs real-time 422P@ML video encoding, audio encoding, and system encoding with no external DRAM. Furthermore, the encoder LSI realizes a 422P@HL video encoder with multi-chip configuration, due to its scalable architecture. This results in a PC-card size 422P@HL encoder with lowest power consumption for portable HDTV codec system.

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Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)

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