将差分接口的每个引脚的数据传输速率加倍的共享数据线技术

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI:10.1109/CICC.2001.929830

F. Hatori, S. Kousai, Y. Unekawa

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引用次数: 5

摘要

提出了一种将差分接口的每引脚数据传输速率提高近一倍的技术。在这种技术中，发送LSI和接收LSI之间的差分传输线的数量与相邻的缓冲区共享，以增加每引脚的传输速率。每个接收器由两个比较器和译码电路组成，译码电路将传输线接收端的信号电压转换为数字数据。在采用CMOS技术制作的测试电路中，数据速率达到了1.1 Gbps/pin。

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Shared data line technique for doubling the data transfer rate per pin of differential interfaces

A technique for almost doubling the data transfer rate per pin of the differential interfaces has been proposed. In this technique the number of the differential transmission lines between transmitter LSI and the receiver LSI are shared with adjacent buffers to increase the transfer rate per pin. Each receiver consists of two comparators and a decoder circuit translates the signal voltage at the receiver end of the transmission line into digital data. A data rate of 1.1 Gbps/pin has been achieved in the fabricated test circuit in CMOS technology.

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来源期刊

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)

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