在0.35 /spl mu/m CMOS中实现厄米解码器IC

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-09 DOI:10.1109/CICC.2001.929782

J. B. Ashbrook, Naresh R Shanbhag, R. Koetter, R. Blahut

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引用次数: 7

摘要

本文提出了第一个厄米解码器的集成电路实现，从而证明了其实际可行性。在相同的域(GF(256))上，与流行的Reed-Solomon (RS)码(n=256)相比，hermite码提供了更大的块长度(n=4080)。这意味着相同速率下的编码增益为0.6 dB。然而，厄米码被认为过于复杂而无法实现，直到最近的算法突破的出现，使得厄米码解码器的复杂性可以与RS码相媲美。基于Koetter的解码算法，芯片架构由16个相互依存的Berlekamp-Massey算法(BMA)块组成。因此，同样的IC也可以用于RS码的解码。该解码器IC采用3.3 V, 0.35 μm，四金属CMOS工艺设计，每n=4080个字块可纠错t=60个错误，速率为400mb /s。该ic原型功耗为3.0 W，时钟为50 MHz

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Implementation of a Hermitian decoder IC in 0.35 /spl mu/m CMOS

This paper presents the first integrated circuit implementation of a Hermitian decoder thereby proving its practical viability. Hermitian codes provide much larger block lengths (n=4080) compared to that of the popular Reed-Solomon (RS) codes (n=256) over the same field (GF(256)). This translates to a coding gain of 0.6 dB for the same rate. However, Hermitian codes were deemed to be too complex to implement until the emergence of a recent algorithmic breakthrough which made the complexity of Hermitian decoders comparable to that of RS codes. Based on Koetter's decoding algorithm, the chip architecture consists of an array of sixteen interdependent Berlekamp-Massey algorithm (BMA) blocks. Thus, the same IC can be used for decoding RS codes as well. The decoder IC is designed in a 3.3 V, 0.35 μm, four-metal CMOS process and can correct up to t=60 errors per block of n=4080 words at a rate of 400 Mb/s. The IC prototype consumes 3.0 W with a 50 MHz clock

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Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)

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