发布求助
文献互助 智能选刊 最新文献

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)最新文献

筛选
英文 中文
PLC advanced technology demonstrator TestChipB PLC先进技术演示器TestChipB
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929725
Theodore Vaida
{"title":"PLC advanced technology demonstrator TestChipB","authors":"Theodore Vaida","doi":"10.1109/CICC.2001.929725","DOIUrl":"https://doi.org/10.1109/CICC.2001.929725","url":null,"abstract":"Rising complexity in ASIC Systems-On-Chip (SOC) has changed the nature of ASIC design and created a tremendous gap between the manufacturing capability and the engineering capability of ASIC designers and users. To solve this, LSI Logic has licensed the Programmable Logic Core (PLC) architecture developed by Adaptive Silicon Inc. This technology will allow ASIC designers to move some portions of the design later in the cycle, even as late as post tape-out. It will also allow for field reprogrammability. A simple test-chip TestChipA containing only the PLC was produced to verify the basic operation of the architecture. This device showed us that the architecture could be produced on an LSI process, but only exposed the physical design portions of the technology to testing. The next step is to develop a complete SOC device utilizing the PLC. This would enable us to rigorously test the methodologies, comb through the documentation and train our engineers to deliver a fully developed and well supported product. This paper describes the PLC architecture as well as the design methodologies needed to develop the test chip named TestChipB.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115534486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Platform design approach for re-configurable network appliances 可重新配置网络设备的平台设计方法
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929728
R. Cmar, R. Pasko, J. Mignolet, G. Vanmeerbeeck, P. Schaumont, S. Vernalde
{"title":"Platform design approach for re-configurable network appliances","authors":"R. Cmar, R. Pasko, J. Mignolet, G. Vanmeerbeeck, P. Schaumont, S. Vernalde","doi":"10.1109/CICC.2001.929728","DOIUrl":"https://doi.org/10.1109/CICC.2001.929728","url":null,"abstract":"The presented platform-based object-oriented modeling concept for system design allowed us to create a networked hardware reconfigurable camera in a 25 man-month schedule with concurrent development of application and target FPGA platform. The developed TCP/IP layer achieves throughput of 2 Mb/s/MHz and the complete application logic consumes 700 mW at 20 MHz.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115275043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
When do we need non-quasistatic CMOS RF-models? 我们什么时候需要非准静态CMOS rf模型?
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929804
E. Gondro, O. Kowarik, G. Knoblinger, P. Klein
{"title":"When do we need non-quasistatic CMOS RF-models?","authors":"E. Gondro, O. Kowarik, G. Knoblinger, P. Klein","doi":"10.1109/CICC.2001.929804","DOIUrl":"https://doi.org/10.1109/CICC.2001.929804","url":null,"abstract":"This paper presents criteria for the onset of NQS effects derived from time transient device simulations and S-parameter measurements. For the first time it has been proved that e.g, a 10 /spl mu/m NMOS transistor can be described up to 27 MHz and a 0.2 /spl mu/m device up to 46 GHz by the quasistatic approach while the accuracy of the description of the inversion layer charge is still 99%.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116102372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Behavioral modeling for timing, noise, and signal integrity analysis 行为建模的时间，噪声，和信号完整性分析
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929800
J. Hayes, L. Wissel
{"title":"Behavioral modeling for timing, noise, and signal integrity analysis","authors":"J. Hayes, L. Wissel","doi":"10.1109/CICC.2001.929800","DOIUrl":"https://doi.org/10.1109/CICC.2001.929800","url":null,"abstract":"I/O behavioral modeling in the form of IBIS models has gained wide acceptance in signal integrity analysis. While the IBIS model accurately represents the characteristics of the output pin at three fixed process corners, it does not model driver delay or account for variations in temperature, supply voltages, and input transition rate. In this paper, we present a behavioral modeling technique that captures driver delay for timing analysis, driver output characteristics for signal integrity, and pre-drive currents for noise and power grid analysis; all are functions of temperature, supply voltages, and input transition rate.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115841530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 0.10 /spl mu/m CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO 一个0.10 /spl mu/m CMOS, 1.2 V, 2 GHz锁相环，增益补偿压控振荡器
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929758
K. Minami, M. Fukaishi, M. Mizuno, H. Onishi, K. Noda, K. Imai, T. Horiuchi, H. Yamaguchi, Takanori Sato, K. Nakamura, Masakazu Yaniashina
{"title":"A 0.10 /spl mu/m CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO","authors":"K. Minami, M. Fukaishi, M. Mizuno, H. Onishi, K. Noda, K. Imai, T. Horiuchi, H. Yamaguchi, Takanori Sato, K. Nakamura, Masakazu Yaniashina","doi":"10.1109/CICC.2001.929758","DOIUrl":"https://doi.org/10.1109/CICC.2001.929758","url":null,"abstract":"This paper describes a 1.2-V, 2-GHz low-jitter phase-locked loop (PLL) using a gain compensation VCO. In order to improve the jitter performance of PLLs, we have developed a new VCO that has a low gain and a linear V-f characteristic. The characteristics of our VCO are achieved by using three V-I converters and blending their different characteristics. The PLL is fabricated in 0.10-/spl mu/m CMOS technology. Its loop filter includes MOS transistors for I/O in order to suppress the influence of gate leakage current. At 1.2 V, 2-GHz operation, measured rms and peak-to-peak jitter of the PLL are 2.8 and 21 ps, respectively.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124109784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Experimental study on MOSFET's flicker noise under switching conditions and modelling in RF applications 开关条件下MOSFET闪烁噪声的实验研究及射频应用建模
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929808
Zhaofeng Zhang, J. Lau
{"title":"Experimental study on MOSFET's flicker noise under switching conditions and modelling in RF applications","authors":"Zhaofeng Zhang, J. Lau","doi":"10.1109/CICC.2001.929808","DOIUrl":"https://doi.org/10.1109/CICC.2001.929808","url":null,"abstract":"The flicker noise mechanism under switching conditions is studied. Experimental results show that the baseband flicker noise is a superposition of upconverted gate flicker noise at each harmonic of the output current. Methods to reduce the flicker noise are discussed. Based on the measured results, the large signal flicker noise model for RF applications under switching conditions is proposed and validated by simulations and measurements. With the proposed model, the noise performance of a single-balanced Gilbert mixer for direct conversion applications is analysed and discussed.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126391863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Mixed-swing methodology for domino logic circuits 多米诺逻辑电路的混合摆动方法学
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929729
Ashoke Rave, L. Carley
{"title":"Mixed-swing methodology for domino logic circuits","authors":"Ashoke Rave, L. Carley","doi":"10.1109/CICC.2001.929729","DOIUrl":"https://doi.org/10.1109/CICC.2001.929729","url":null,"abstract":"In this paper we present a multiplier-accumulator (MAC) implemented in mixed-swing dual-rail domino logic. The performance in the presence of noise and on-chip coupling is studied. A completely on-chip voltage regulation technique which adjusts the degree of voltage regulation in the MAC in the face of process induced delay variations so as to minimize energy dissipation while always guaranteeing the target operating frequency is also described. Measurements for a commercial 0.5 /spl mu/m CMOS process demonstrate that the mixed-swing methodology with series regulation is a viable low power high speed solution for multiplier circuits.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126820704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A -94 dBc/Hz@100 kHz, fully-integrated, 5-GHz, CMOS VCO with 18% tuning range for Bluetooth applications -94 dBc/Hz@100 kHz，完全集成，5 ghz, CMOS VCO, 18%调谐范围，适用于蓝牙应用
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929755
C. Samori, S. Levantino, V. Boccuzzi
{"title":"A -94 dBc/Hz@100 kHz, fully-integrated, 5-GHz, CMOS VCO with 18% tuning range for Bluetooth applications","authors":"C. Samori, S. Levantino, V. Boccuzzi","doi":"10.1109/CICC.2001.929755","DOIUrl":"https://doi.org/10.1109/CICC.2001.929755","url":null,"abstract":"A 5-GHz, fully monolithic voltage-controlled oscillator (VCO) for Bluetooth wireless transceivers is demonstrated in a 0.25 /spl mu/m CMOS technology using accumulation mode varactors and spiral inductors. An 18% tuning range was measured for only 2.5 V tuning-voltage variation. The phase noise was -94 dBc/Hz at 100 kHz frequency offset with 40 kHz 1/f/sup 3/ corner frequency. These low values are limited by the up-conversion of flicker noise due to varactor amplitude-to-frequency conversion and to the modulation of the varactor bias point. This explanation is verified by simulations and measurements. The circuit draws 5.5 mA from a 2.5 V power supply.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128104655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 67
Embedded anti-aliasing in switched-capacitor ladder filters 开关电容梯形滤波器的嵌入式抗混叠
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929714
Shin'ichiro Azuma, S. Kawama, K. Iizuka, M. Miyamoto, D. Senderowicz
{"title":"Embedded anti-aliasing in switched-capacitor ladder filters","authors":"Shin'ichiro Azuma, S. Kawama, K. Iizuka, M. Miyamoto, D. Senderowicz","doi":"10.1109/CICC.2001.929714","DOIUrl":"https://doi.org/10.1109/CICC.2001.929714","url":null,"abstract":"A combination of continuous-time and switched-capacitor integrators in a simulated LC loss-less ladder yields a response with suppressed aliasing without using continuous-time pre-filtering. Fabricated in a 0.35-/spl mu/m CMOS process, a fifth-order Cauer low-pass filter has a cutoff frequency of 1.92 MHz and aliasing suppression of better than 40 dB. Without using any tuning mechanism, /spl plusmn/10% accuracy of the cut-off frequency is achieved. It consumes 3.7 mA at 1.8-V power supply in a die-area of 0.27 mm/sup 2/.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"06 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127353230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 12-bit integrated analog front-end for broadband wireline networks 用于宽带有线网络的12位集成模拟前端
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI: 10.1109/CICC.2001.929737
I. Mehr, P. C. Maulik, D. Paterson
{"title":"A 12-bit integrated analog front-end for broadband wireline networks","authors":"I. Mehr, P. C. Maulik, D. Paterson","doi":"10.1109/CICC.2001.929737","DOIUrl":"https://doi.org/10.1109/CICC.2001.929737","url":null,"abstract":"An integrated transceiver for broadband wireline networks is presented. The transceiver includes a receive data path, a transmit datapath, and auxiliary functions including serial port interface, clock and reference generation blocks, and voltage regulator control circuitry. The receive data path provides constant input impedance and is composed of two variable gain amplifier (VGA) blocks, an analog 4-pole filter, a 12-bit analog-to-digital converter (ADC) sampling at 32 MHz, and a digital high-pass filter. The transmit data path contains digital interpolation filters and a 12-bit digital-to-analog converter (DAC) sampling at 128 MHz. The chip was implemented in double-poly triple-metal 0.35 /spl mu/m CMOS technology. Measured performance for both receive and transmit data paths meets target specifications with no noticeable crosstalk.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130749669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信