A 12-bit integrated analog front-end for broadband wireline networks

I. Mehr, P. C. Maulik, D. Paterson
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引用次数: 15

Abstract

An integrated transceiver for broadband wireline networks is presented. The transceiver includes a receive data path, a transmit datapath, and auxiliary functions including serial port interface, clock and reference generation blocks, and voltage regulator control circuitry. The receive data path provides constant input impedance and is composed of two variable gain amplifier (VGA) blocks, an analog 4-pole filter, a 12-bit analog-to-digital converter (ADC) sampling at 32 MHz, and a digital high-pass filter. The transmit data path contains digital interpolation filters and a 12-bit digital-to-analog converter (DAC) sampling at 128 MHz. The chip was implemented in double-poly triple-metal 0.35 /spl mu/m CMOS technology. Measured performance for both receive and transmit data paths meets target specifications with no noticeable crosstalk.
用于宽带有线网络的12位集成模拟前端
介绍了一种用于宽带有线网络的集成收发器。收发器包括接收数据路径、发送数据路径和辅助功能,包括串口接口、时钟和参考生成块以及稳压控制电路。接收数据路径提供恒定的输入阻抗,由两个可变增益放大器(VGA)模块、一个模拟4极滤波器、一个32 MHz采样的12位模数转换器(ADC)和一个数字高通滤波器组成。传输数据路径包含数字插值滤波器和一个128 MHz采样的12位数模转换器(DAC)。该芯片采用双聚三金属0.35 /spl mu/m CMOS技术实现。接收和发送数据路径的测量性能均符合目标规格,没有明显的串扰。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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