Mixed-swing methodology for domino logic circuits

Abstract

In this paper we present a multiplier-accumulator (MAC) implemented in mixed-swing dual-rail domino logic. The performance in the presence of noise and on-chip coupling is studied. A completely on-chip voltage regulation technique which adjusts the degree of voltage regulation in the MAC in the face of process induced delay variations so as to minimize energy dissipation while always guaranteeing the target operating frequency is also described. Measurements for a commercial 0.5 /spl mu/m CMOS process demonstrate that the mixed-swing methodology with series regulation is a viable low power high speed solution for multiplier circuits.