PLC advanced technology demonstrator TestChipB

Abstract

Rising complexity in ASIC Systems-On-Chip (SOC) has changed the nature of ASIC design and created a tremendous gap between the manufacturing capability and the engineering capability of ASIC designers and users. To solve this, LSI Logic has licensed the Programmable Logic Core (PLC) architecture developed by Adaptive Silicon Inc. This technology will allow ASIC designers to move some portions of the design later in the cycle, even as late as post tape-out. It will also allow for field reprogrammability. A simple test-chip TestChipA containing only the PLC was produced to verify the basic operation of the architecture. This device showed us that the architecture could be produced on an LSI process, but only exposed the physical design portions of the technology to testing. The next step is to develop a complete SOC device utilizing the PLC. This would enable us to rigorously test the methodologies, comb through the documentation and train our engineers to deliver a fully developed and well supported product. This paper describes the PLC architecture as well as the design methodologies needed to develop the test chip named TestChipB.