{"title":"适用于片上系统的CMOS工艺兼容ie-Flash(反栅电极Flash)技术","authors":"S. Shukuri, K. Yanagisawa, K. Ishibashi","doi":"10.1109/CICC.2001.929750","DOIUrl":null,"url":null,"abstract":"A highly reliable single-poly flash technology named ie-Flash (inverse gate electrode Flash), which can be embedded in the common 0.14 /spl mu/m CMOS process without any process modifications, has been developed. The ie-Flash cell consists of two elementary cells for OR-logical reading, resulting in significant improvement of reliability. 5 V programming with 1 ms duration and 1.2 V-read operation of 35 bit memory modules fabricated by a 0.14 /spl mu/m CMOS process is demonstrated.","PeriodicalId":101717,"journal":{"name":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"CMOS process compatible ie-Flash (inverse gate electrode Flash) technology for system-on-a-chip\",\"authors\":\"S. Shukuri, K. Yanagisawa, K. Ishibashi\",\"doi\":\"10.1109/CICC.2001.929750\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A highly reliable single-poly flash technology named ie-Flash (inverse gate electrode Flash), which can be embedded in the common 0.14 /spl mu/m CMOS process without any process modifications, has been developed. The ie-Flash cell consists of two elementary cells for OR-logical reading, resulting in significant improvement of reliability. 5 V programming with 1 ms duration and 1.2 V-read operation of 35 bit memory modules fabricated by a 0.14 /spl mu/m CMOS process is demonstrated.\",\"PeriodicalId\":101717,\"journal\":{\"name\":\"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-05-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2001.929750\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2001.929750","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
摘要
开发了一种高可靠性的单聚flash技术,即ie-Flash(逆栅电极flash),该技术无需任何工艺修改即可嵌入到常见的0.14 /spl μ m CMOS工艺中。ie-Flash单元由两个基本单元组成,用于or逻辑读取,从而显著提高了可靠性。对采用0.14 /spl μ m CMOS工艺制作的35位内存模块进行了5v编程,编程时间为1ms,读取操作为1.2 V。
CMOS process compatible ie-Flash (inverse gate electrode Flash) technology for system-on-a-chip
A highly reliable single-poly flash technology named ie-Flash (inverse gate electrode Flash), which can be embedded in the common 0.14 /spl mu/m CMOS process without any process modifications, has been developed. The ie-Flash cell consists of two elementary cells for OR-logical reading, resulting in significant improvement of reliability. 5 V programming with 1 ms duration and 1.2 V-read operation of 35 bit memory modules fabricated by a 0.14 /spl mu/m CMOS process is demonstrated.