A differential bipolar quasi-passive cyclic digital-to-analog converter with 4.416 MSps conversion rate and -77 dB THD

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI:10.1109/CICC.2001.929747

M. Moussavi, R. Mason, C. Plett

引用次数: 8

Abstract

Cyclic Digital-to-Analog Converters (DACs) can provide low power alternatives to current steering DACs for medium conversion rates. A cyclic DAC capable of achieving lite-rate DSL performance for downstream is presented in this paper. With the help of a differential bipolar architecture, the DAC delivers close to 12 bits of linearity at 4.416 MS/s conversion rate. The cyclic D/A converter, implemented in a 0.35-/spl mu/m double-poly CMOS technology, dissipates only 10 mW.

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差分双极准无源循环数模转换器，转换速率为4.416 MSps, THD为-77 dB

循环数模转换器(dac)可以为中等转换速率的当前转向dac提供低功耗替代方案。本文提出了一种能够实现终身速率DSL下行性能的循环DAC。在差分双极架构的帮助下，DAC以4.416 MS/s的转换速率提供接近12位的线性度。循环D/A转换器采用0.35-/spl mu/m双聚CMOS技术，功耗仅为10 mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)

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