A fast-lock mixed-mode DLL using a 2-b SAR algorithm

Abstract

In this paper, a fast-lock mixed-mode DLL (MMDLL) is presented. The digital part of the MMDLL utilizes a 2-b SAR algorithm to achieve short lock time compared to the conventional RDLL, CDLL and SARDLL, while the analog part helps to reduce the static phase error and improve the output clock jitter. The measured output clock rms, peak-to-peak jitter and static phase error are 6.6 ps, 47 ps and 12.4 ps, respectively at 100 MHz and the power consumption is 15.8 mW in the locked state at 2.7 V supply voltage. The maximum lock time is 13.5 clock cycles when the static phase error is within 1 LSB (156 ps).