单片10.7 gb/s FEC编解码LSI采用时复用RS解码器

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) Pub Date : 2001-05-06 DOI:10.1109/CICC.2001.929778

K. Seki, Kousuke Mikami, M. Baba, N. Shinohara, S. Suzuki, H. Tezuka, S. Uchino, N. Okada, Y. Kakinuma, A. Katayama

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引用次数: 12

摘要

介绍了一种用于光传输系统的10.7 Gb/s吞吐量FEC(前向纠错)编解码LSI。为了降低功耗和逻辑尺寸，FEC编解码器采用时复用Reed-Solomon (RS)解码器，该解码器由4个RS码字共享，处理5个并行数字。时间复用RS解码器只需要传统解码器58%的门和75%的功耗。因此，采用0.18 /spl mu/m CMOS技术，编解码器实现了仅3.31 W的低功耗和仅1.1 Mgates的低栅极计数。

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Single-chip 10.7 gb/s FEC codec LSI using time-multiplexed RS decoder

This paper describes a 10.7 Gb/s throughput FEC (Forward Error Correction) codec LSI for optical transmission systems. In order to reduce the power consumption and logic size, the FEC codec uses a time-multiplexed Reed-Solomon (RS) decoder, which is shared among 4 RS codewords and processes 5 parallel digits. The time-multiplexed RS decoder requires only 58% of the gates and 75% of the power consumption of the conventional decoder. As a result, the codec achieves a low power consumption of only 3.31 W and a low gate count of only 1.1 Mgates using 0.18 /spl mu/m CMOS technology.

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Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)

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