Technical digest. International Electron Devices Meeting最新文献_第8页

Proposed universal relationship between dielectric breakdown and dielectric constant 提出介电击穿与介电常数的普遍关系

Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175919

J. McPherson, J. Kim, A. Shanware, H. Mogul, J. Rodriguez

{"title":"Proposed universal relationship between dielectric breakdown and dielectric constant","authors":"J. McPherson, J. Kim, A. Shanware, H. Mogul, J. Rodriguez","doi":"10.1109/IEDM.2002.1175919","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175919","url":null,"abstract":"Dielectrics with high dielectric constant k will likely be required for future replacement of conventional SiO/sub 2/ gate dielectric. Physical models are needed which describe the reliability tradeoffs associated with the high-k material selection. In this paper we report on a fundamental relationship existing between the dielectric breakdown E/sub bd/ and dielectric constant k. An approximate E/sub bd/ /spl sim/ (k )/sup -1/2/ relation is found and seems to be universal, i.e., the relation holds over nearly two decades of dielectric constant. A physics-based model has been developed to understand this critically important relationship. The good fit of the physical model (with no adjustable parameters) to the experimental data suggests that the local electric field (Lorentz-relation/Mossotti-field) in these high-k materials plays a very important role in the observed E/sub bd/ /spl sim/ (k)/sup -1/2/ behavior. The very high local electric field (in high-k materials) tends to distort/weaken polar molecular-bonds thereby lowering the enthalpy of activation required for bond breakage by standard Boltzmann processes.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"41 5 1","pages":"633-636"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89158910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 80

A VLSI compatible conducting polymer composite based "electronic nose" chip 一种兼容VLSI的基于导电聚合物复合材料的“电子鼻”芯片

Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175885

N. Lewis

引用次数: 3

Silicon on Depletion Layer FET (SODEL FET) for sub-50 nm high performance CMOS applications: novel channel and S/D profile engineering schemes by selective Si epitaxial growth technology 用于50纳米以下高性能CMOS应用的损耗层场效应晶体管(SODEL FET):采用选择性硅外延生长技术的新型通道和S/D轮廓工程方案

Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175925

S. Inaba, K. Miyano, A. Hokazono, K. Ohuchi, I. Mizushima, H. Oyamatsu, Y. Tsunashima, Y. Toyoshima, H. Ishiuchi

{"title":"Silicon on Depletion Layer FET (SODEL FET) for sub-50 nm high performance CMOS applications: novel channel and S/D profile engineering schemes by selective Si epitaxial growth technology","authors":"S. Inaba, K. Miyano, A. Hokazono, K. Ohuchi, I. Mizushima, H. Oyamatsu, Y. Tsunashima, Y. Toyoshima, H. Ishiuchi","doi":"10.1109/IEDM.2002.1175925","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175925","url":null,"abstract":"In this paper, novel channel & S/D profile engineering schemes are proposed for sub-50 nm bulk CMOS applications. These devices, referred to as \"Silicon On DEpletion Layer (SODEL) FETs\", have the depletion layer beneath the channel region, which works as an insulator like a buried oxide (BOX) in SOI MOSFET. The device design concepts of SODEL FET were confirmed by hardware fabrication with 100 nm node CMOS technology. By using selective Si epitaxy for the channel region, junction capacitance (Cj) has been reduced to less than about 1/2/spl sim/1/3 of that in conventional 100 nm node CMOS. i.e., Cj(area) /spl sim/ 0.73 fF//spl mu/m/sup 2/, and Cj (gate edge perimeter) /spl sim/ 0.19 fF//spl mu/m both in nFET & pFET at Vbias = 0.0 V. The body effect /spl gamma/ is also reduced to less than 0.02 V/sup 1/2/. Nevertheless, high current drives of 886 /spl mu/A//spl mu/m (Ioff = 15 nA//spl mu/m) in nFET and -320 /spl mu/A//spl mu/m (Ioff = 10 nA//spl mu/m) in pFET have been achieved in SODEL CMOS with |Vdd| = 1.2 V. Therefore, high speed circuit design can be realized by the combination of SODEL FETs and bulk FETs on the same chip in 70 nm node generation and beyond.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"1 1","pages":"659-662"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88304473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A CMOS magnetic latch with extremely high resolution 具有极高分辨率的CMOS磁锁存器

Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175984

Z.Q. Li, X.W. Sun

引用次数: 4

A 90 nm generation copper dual damascene technology with ALD TaN barrier 90纳米代铜双大马士革技术与ALD TaN屏障

Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175913

C.H. Peng, C. Hsieh, C.L. Huang, J.C. Lin, M. Tsai, M.W. Lin, C. Chang, W. Shue, M. Liang

引用次数: 7

Tunable work function dual metal gate technology for bulk and non-bulk CMOS 块体和非块体CMOS的可调谐工作功能双金属栅极技术

Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175852

Jae-Hoon Lee, H. Zhong, You-Seok Suh, G. Heuss, J. Gurganus, Bei Chen, V. Misra

引用次数: 31

Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175799

D. Ielmini, A. Spinelli, A. Lacaita, M. van Duuren

引用次数: 14

Integrated surface-micromachined z-axis frame microgyroscope 集成表面微加工z轴框架微陀螺仪

Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175813

Moorthi Palaniapan, Roger T. Howe, John Yasaitis

引用次数: 10

High efficient 850 nm and 1,310 nm multiple quantum well SiGe/Si heterojunction phototransistors with 1.25 plus GHz bandwidth (850 nm) 高效率850 nm和1310 nm多量子阱SiGe/Si异质结光电晶体管，1.25 + GHz带宽(850 nm)

Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175837

Z. Pei, C. Liang, L. Lai, Y. Tseng, Y. Hsu, P. Chen, S. Lu, C.M. Liu, M. Tsai, C. Liu

引用次数: 17

High performance 40 nm nMOSFETs with HfO2 gate dielectric and polysilicon damascene gate 高性能40纳米nmosfet与HfO2栅极电介质和多晶硅damascene栅极

Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175870

B. Tavel, X. Garros, T. Skotnicki, F. Martin, C. Leroux, D. Bensahel, M. Semeria, Y. Morand, J. Damlencourt, S. Descombes, F. Leverd, Y. Le-Friec, P. Leduc, M. Rivoire, S. Jullian, R. Pantel

引用次数: 10