High performance 40 nm nMOSFETs with HfO2 gate dielectric and polysilicon damascene gate

B. Tavel, X. Garros, T. Skotnicki, F. Martin, C. Leroux, D. Bensahel, M. Semeria, Y. Morand, J. Damlencourt, S. Descombes, F. Leverd, Y. Le-Friec, P. Leduc, M. Rivoire, S. Jullian, R. Pantel
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引用次数: 10

Abstract

We report on 40 nm nMOS transistors with HfO/sub 2/ dielectric and polySi gate integrated into a damascene structure. We fabricated HfO/sub 2/ ALD layers with EOT down to 15 /spl Aring/, exhibiting leakage current more than two decades lower than SiO/sub 2/. Small mobility degradation on 2 nm EOT nMOSFETs was observed leading to the best performances (Ion= 680 /spl mu/A//spl mu/m @ Ioff=230 nA//spl mu/m) ever obtained with HfO/sub 2/ and polySi electrodes.
高性能40纳米nmosfet与HfO2栅极电介质和多晶硅damascene栅极
我们报道了将HfO/sub - 2/介电介质和多晶硅栅极集成到大马士革结构中的40 nm nMOS晶体管。我们制备了EOT低至15 /spl的HfO/sub - 2/ ALD层,其泄漏电流比SiO/sub - 2/低20多年。在2nm EOT nmosfet上观察到较小的迁移率下降,导致HfO/ sub2 /和polySi电极获得了最佳性能(离子= 680 /spl mu/A//spl mu/m @ Ioff=230 nA//spl mu/m)。
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CiteScore
4.50
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