Silicon on Depletion Layer FET (SODEL FET) for sub-50 nm high performance CMOS applications: novel channel and S/D profile engineering schemes by selective Si epitaxial growth technology

Abstract

In this paper, novel channel & S/D profile engineering schemes are proposed for sub-50 nm bulk CMOS applications. These devices, referred to as "Silicon On DEpletion Layer (SODEL) FETs", have the depletion layer beneath the channel region, which works as an insulator like a buried oxide (BOX) in SOI MOSFET. The device design concepts of SODEL FET were confirmed by hardware fabrication with 100 nm node CMOS technology. By using selective Si epitaxy for the channel region, junction capacitance (Cj) has been reduced to less than about 1/2/spl sim/1/3 of that in conventional 100 nm node CMOS. i.e., Cj(area) /spl sim/ 0.73 fF//spl mu/m/sup 2/, and Cj (gate edge perimeter) /spl sim/ 0.19 fF//spl mu/m both in nFET & pFET at Vbias = 0.0 V. The body effect /spl gamma/ is also reduced to less than 0.02 V/sup 1/2/. Nevertheless, high current drives of 886 /spl mu/A//spl mu/m (Ioff = 15 nA//spl mu/m) in nFET and -320 /spl mu/A//spl mu/m (Ioff = 10 nA//spl mu/m) in pFET have been achieved in SODEL CMOS with |Vdd| = 1.2 V. Therefore, high speed circuit design can be realized by the combination of SODEL FETs and bulk FETs on the same chip in 70 nm node generation and beyond.