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Transistors with dual work function metal gates by single full silicidation (FUSI) of polysilicon gates 采用多晶硅栅极的单次全硅化(FUSI)方法制备具有双功功能金属栅极的晶体管
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175854
W. Maszara, Z. Krivokapic, P. King, J. Goo, M. Lin
{"title":"Transistors with dual work function metal gates by single full silicidation (FUSI) of polysilicon gates","authors":"W. Maszara, Z. Krivokapic, P. King, J. Goo, M. Lin","doi":"10.1109/IEDM.2002.1175854","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175854","url":null,"abstract":"Metal gate electrodes with two different work functions, /spl sim/4.5 and /spl sim/4.9 eV for NMOS and PMOS, respectively, were obtained by single-step full silicidation of poly gates. Reduction of polysilicon depletion was /spl sim/0.25 nm. Pile-up of arsenic at the NMOS dielectric is believed responsible for NiSi work function modification. Metal gate may offer little or no gate current reduction for the same T/sub oxinv/ as poly gate.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"32 1 1","pages":"367-370"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90217867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 72
A study of subband structure and transport of two-dimensional holes in strained-Si p-MOSFETs using full-band modeling 用全带模型研究应变si - p- mosfet中二维空穴的子带结构和输运
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175941
H. Nakatsuji, Y. Kamakura, K. Taniguchi
{"title":"A study of subband structure and transport of two-dimensional holes in strained-Si p-MOSFETs using full-band modeling","authors":"H. Nakatsuji, Y. Kamakura, K. Taniguchi","doi":"10.1109/IEDM.2002.1175941","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175941","url":null,"abstract":"The quantum confinement of the two-dimensional (2D) hole gas in the inversion layer of strained-Si p-MOSFETs is investigated theoretically. The hole mobility enhancement was found to originate from the suppressed inter-band scattering due to subband splitting and the reduced effective mass in the lowest subband with strain.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"28 1","pages":"727-730"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83708886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Device performance of sub-50 nm CMOS with ultra-thin plasma nitrided gate dielectrics 采用超薄等离子体氮化栅极电介质的50 nm以下CMOS器件性能
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175923
S. Inaba, T. Shimizu, S. Mori, K. Sekine, K. Saki, H. Suto, H. Fukui, M. Nagamine, M. Fujiwara, T. Yamamoto, M. Takayanagi, I. Mizushima, K. Okano, S. Matsuda, H. Oyamatsu, Y. Tsunashima, S. Yamada, Y. Toyoshima, H. Ishiuchi
{"title":"Device performance of sub-50 nm CMOS with ultra-thin plasma nitrided gate dielectrics","authors":"S. Inaba, T. Shimizu, S. Mori, K. Sekine, K. Saki, H. Suto, H. Fukui, M. Nagamine, M. Fujiwara, T. Yamamoto, M. Takayanagi, I. Mizushima, K. Okano, S. Matsuda, H. Oyamatsu, Y. Tsunashima, S. Yamada, Y. Toyoshima, H. Ishiuchi","doi":"10.1109/IEDM.2002.1175923","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175923","url":null,"abstract":"In this paper, the physical and electrical characteristics of ultra-thin plasma nitrided gate dielectrics are reported, aiming for sub-50 nm gate length CMOS applications. The impact of plasma nitridation conditions on DC characteristics was investigated extensively by changing nitrogen plasma pressure, plasma immersion time, or plasma generation power. NBTI has been also investigated and the lifetime at 105/spl deg/C and 0.85 V operation is estimated to be about 10 years. The final current drives of 690 /spl mu/A//spl mu/m for nFET and 301 /spl mu/A//spl mu/m for pFET at Vdd = 0.85 V (Ioff = 100 nA//spl mu/m) have been achieved in sub-50 nm CMOS with optimized plasma nitrided gate dielectric with EOT <1.2 nm.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"23 1","pages":"651-654"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85830829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Novel SOI wafer engineering using low stress and high mobility CMOSFET with <100>-channel for embedded RF/analog applications 新颖的SOI晶圆工程，采用低应力和高迁移率CMOSFET与-通道，用于嵌入式射频/模拟应用
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175926
T. Matsumoto, S. Maeda, H. Dang, T. Uchida, K. Ota, Y. Hirano, H. Sayama, T. Iwamatsu, T. Ipposhi, H. Oda, S. Maegawa, Y. Inoue, T. Nishimura
{"title":"Novel SOI wafer engineering using low stress and high mobility CMOSFET with <100>-channel for embedded RF/analog applications","authors":"T. Matsumoto, S. Maeda, H. Dang, T. Uchida, K. Ota, Y. Hirano, H. Sayama, T. Iwamatsu, T. Ipposhi, H. Oda, S. Maegawa, Y. Inoue, T. Nishimura","doi":"10.1109/IEDM.2002.1175926","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175926","url":null,"abstract":"For high performance RF/analog and logic device technology, novel SOI wafer engineering featuring <100>-channel SOI CMOSFET with high-resistivity substrate is proposed. Mobility of PMOSFET is improved about 16% by changing a channel direction from <110> to <100>. Moreover, the reduction of the drive current in narrow channel PMOSFET is suppressed. The maximum oscillation frequency (f/sub max/) for NMOSFET is improved around 7% by changing the buried oxide (BOX) thickness from 400 nm to 150 nm because the self-heating effect is suppressed, and is improved around 5% by changing the substrate resistivity from 10 /spl Omega/cm to 1000 /spl Omega/cm because the power loss is reduced. In this work, the wafer engineering which consists of 1) <100>-channel, 2) optimization of BOX, and 3) high resistivity substrate, is proposed to improve the RF performance of the CMOSFET.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"186 1","pages":"663-666"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83045839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
QDAME simulation of 7.5 nm double-gate Si nFETs with differing access geometries 不同存取几何形状的7.5 nm双栅Si非场效应管的QDAME模拟
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175938
S. Laux, A. Kumar, M. Fischetti
{"title":"QDAME simulation of 7.5 nm double-gate Si nFETs with differing access geometries","authors":"S. Laux, A. Kumar, M. Fischetti","doi":"10.1109/IEDM.2002.1175938","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175938","url":null,"abstract":"We describe QDAME, a new device simulation program which solves self-consistently the Poisson and Schrodinger equations in two space dimensions under the approximation of ballistic transport. The effects of differing access geometries on 7.5 nm double-gate Si FETs are discussed.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"50 1","pages":"715-718"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79127606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
An organic optical bistable switch 一种有机光双稳开关
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175985
J. Xue, S. Forrest
{"title":"An organic optical bistable switch","authors":"J. Xue, S. Forrest","doi":"10.1109/IEDM.2002.1175985","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175985","url":null,"abstract":"We demonstrate an organic optical bistable switch by integrating an organic photodetector on top of a transparent electrophosphorescent organic light-emitting diode. Optical bistability is achieved with an external field-effect transistor providing positive feedback. This integrated device has potential applications for automatic brightness control, image-retaining displays, and other photonic logic circuits.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"65 1","pages":"913-915"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81320365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Variation in natural threshold voltage of NVM circuits due to dopant fluctuations and its impact on reliability 掺杂物引起的NVM电路自然阈值电压变化及其对可靠性的影响
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175896
D. Burnett, J. Higman, A. Hoefler, C.-N.B. Li, P. Kuhn
{"title":"Variation in natural threshold voltage of NVM circuits due to dopant fluctuations and its impact on reliability","authors":"D. Burnett, J. Higman, A. Hoefler, C.-N.B. Li, P. Kuhn","doi":"10.1109/IEDM.2002.1175896","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175896","url":null,"abstract":"The statistical distribution of the natural threshold voltage (V/sub T0/) of 512k-bit NVM circuit arrays has been studied for two different technologies. The major source of the V/sub T0/ variation is dopant fluctuations of the NVM well. An analytical model for the dopant fluctuations provides excellent agreement with the measured circuit V/sub T0/ variation and NVM cell mismatch for both technologies. The reliability implications of the V/sub T0/ variation are considered using charge leakage models for data retention.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"43 1","pages":"529-532"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83490143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Junction defects of self-aligned, excimer-laser-annealed poly-Si TFTs 自对准准激光退火多晶硅tft的结缺陷
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175906
K.C. Park, S.H. Jung, M.C. Lee, S.H. Kang, K. Moon, M. Han
{"title":"Junction defects of self-aligned, excimer-laser-annealed poly-Si TFTs","authors":"K.C. Park, S.H. Jung, M.C. Lee, S.H. Kang, K. Moon, M. Han","doi":"10.1109/IEDM.2002.1175906","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175906","url":null,"abstract":"Reports residual ion implantation damage at source/drain junctions of self-aligned, excimer-laser-annealed poly-Si TFTs. TEM observation revealed that the implantation damage was not completely annealed at the junction by excimer laser annealing because the laser irradiation intensity decreased remarkably at the junction due to diffraction of laser beam at gate electrode edge. Field effect mobility of poly-Si TFTs was degraded by the crystalline defects at the junction particularly for short channel devices. We eliminated the junction defects by oblique-incidence excimer laser annealing and improved the characteristics of poly-Si TFTs.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"31 1","pages":"573-576"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84485087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improved current performance of CMOSFETs with nitrogen incorporated HfO2-Al2O3 laminate gate dielectric 氮掺杂HfO2-Al2O3层压栅电介质改善了cmosfet的电流性能
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175971
Hyung-Seok Jung, Yun-seok Kim, Jong Pyo Kim, Jung Hyoung Lee, Jong-Ho Lee, N. Lee, Ho-Kyu Kang, K. Suh, H. Ryu, C. Oh, Young-Wug Kim, K. Cho, H. Baik, Youngsu Chung, H. Chang, D. Moon
{"title":"Improved current performance of CMOSFETs with nitrogen incorporated HfO2-Al2O3 laminate gate dielectric","authors":"Hyung-Seok Jung, Yun-seok Kim, Jong Pyo Kim, Jung Hyoung Lee, Jong-Ho Lee, N. Lee, Ho-Kyu Kang, K. Suh, H. Ryu, C. Oh, Young-Wug Kim, K. Cho, H. Baik, Youngsu Chung, H. Chang, D. Moon","doi":"10.1109/IEDM.2002.1175971","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175971","url":null,"abstract":"For the first time, we integrated poly-Si gate CMOSFETs with nitrogen incorporated HfO/sub 2/-Al/sub 2/O/sub 3/ laminate (HfAlON) as gate dielectrics. Both low gate leakage currents (0.1 mA/cm/sup 2/ at V/sub g/=+1.0 V) and low EOT (15.6 /spl Aring/) sufficiently satisfy the specifications (EOT=12/spl sim/20 /spl Aring/, J/sub g/=2.2 mA/cm/sup 2/) estimated by ITRS for low power applications. By in-situ 3 step post-deposition annealing, approximately 17 at.% nitrogen is incorporated at the HfAlON/Si interface. In-situ 3 step post-deposition annealing decreases metallic Hf bonding, which exists at the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate/Si interface. As a result, we can suppress C-V hysteresis and improve current performance. Finally, well-behaved 100 nm CMOSFET devices are achieved. The measured saturation currents at 1.2 V V/sub dd/ are 585 /spl mu//spl Aring///spl mu/m (I/sub off/= 10 nA//spl mu/m) for nMOSFET and 265 /spl mu/A//spl mu/m (I/sub off/=10 nA//spl mu/m) for pMOSFET, which are approximately 80% of those of nitrided SiO/sub 2/. In terms of I/sub on/-I/sub off/ characteristics of n/pMOSFETs, these results represent the best current performance compared with previous reports for poly-Si gate CMOSFETs with high-k gate dielectrics.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"56 1","pages":"853-856"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90592305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Does source-to-drain tunneling limit the ultimate scaling of MOSFETs? 源极-漏极隧道是否限制了mosfet的最终缩放?
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175936
Jing Wang, M. Lundstrom
{"title":"Does source-to-drain tunneling limit the ultimate scaling of MOSFETs?","authors":"Jing Wang, M. Lundstrom","doi":"10.1109/IEDM.2002.1175936","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175936","url":null,"abstract":"By using the non-equilibrium Green's function approach, we report a comprehensive and rigorous study of source-to-drain tunneling in MOSFETs at the scaling limit. The dependence of source-to-drain tunneling on channel length, electrostatics, ambient temperature and scattering is examined, and the effects of source-to-drain tunneling on device characteristics and design issues are explored as well. The results show that source-to-drain tunneling does set an ultimate scaling limit but that this limit is well below 10 nm.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"9 1","pages":"707-710"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85511663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 147
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