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Nitride-sandwiched-oxide gate insulator for low power CMOS 用于低功耗CMOS的氮夹氧化物栅极绝缘体
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175975
D. Ishikawa, S. Sakai, K. Katsuyama, A. Hiraiwa
{"title":"Nitride-sandwiched-oxide gate insulator for low power CMOS","authors":"D. Ishikawa, S. Sakai, K. Katsuyama, A. Hiraiwa","doi":"10.1109/IEDM.2002.1175975","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175975","url":null,"abstract":"A gate insulator with a novel nitride-sandwiched oxide (NSO) structure was formed by successive NO and plasma nitridation steps. This approach reduced the leakage current to 15% of the oxide value, while enhancing the electron mobility by 15%. NSO also has high dielectric reliability and almost completely blocks B penetration in a PMOS device. Our experiments have confirmed that NSO is a very promising technology for forming gate insulators in low-power CMOS devices in the 100-nm to 80-nm node.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"92 1","pages":"869-872"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76389191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Dual-metal gate CMOS with HfO2 gate dielectric 具有HfO2栅极介质的双金属栅极CMOS
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175871
S. Samavedam, L. La, J. Smith, S. Dakshina-Murthy, E. Luckowski, J. Schaeffer, M. Zavala, R. Martin, V. Dhandapani, D. Triyoso, H. Tseng, P. Tobin, D. Gilmer, C. Hobbs, W. Taylor, J. Grant, R. Hegde, J. Mogab, C. Thomas, P. Abramowitz, M. Moosa, J. Conner, J. Jiang, V. Arunachalarn, M. Sadd, B. Nguyen, B. White
{"title":"Dual-metal gate CMOS with HfO2 gate dielectric","authors":"S. Samavedam, L. La, J. Smith, S. Dakshina-Murthy, E. Luckowski, J. Schaeffer, M. Zavala, R. Martin, V. Dhandapani, D. Triyoso, H. Tseng, P. Tobin, D. Gilmer, C. Hobbs, W. Taylor, J. Grant, R. Hegde, J. Mogab, C. Thomas, P. Abramowitz, M. Moosa, J. Conner, J. Jiang, V. Arunachalarn, M. Sadd, B. Nguyen, B. White","doi":"10.1109/IEDM.2002.1175871","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175871","url":null,"abstract":"We report for the first time on a novel dual-metal gate CMOS integration on HfO/sub 2/ gate dielectric using TiN (PMOS) and TaSiN (NMOS) gate electrodes. Compared to a single metal integration, the dual-metal integration does not degrade gate leakage, mobility and charge trapping behavior. Promising preliminary TDDB data were obtained from dual-metal gate MOSFETs, while still delivering much improved gate leakage (10/sup 4/ - 10/sup 5/ X better than SiO/sub 2/).","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"28 1","pages":"433-436"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76749912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
Demonstration of a 4 Mb, high density ferroelectric memory embedded within a 130 nm, 5 LM Cu/FSG logic process 在130 nm, 5 LM Cu/FSG逻辑过程中嵌入4mb高密度铁电存储器的演示
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175897
T. Moise, S. Summerfelt, H. McAdams, S. Aggarwal, K. Udayakumar, F. Celii, J.S. Martin, G. Xing, L. Hall, K. Taylor, T. Hurd, J. Rodriguez, K. Remack, M. D. Khan, K. Boku, G. Stacey, M. Yao, M. Albrecht, E. Zielinski, M. Thakre, S. Kuchimanchi, A. Thomas, B. McKee, J. Rickes, A. Wang, J. Grace, J. Fong, D. Lee, C. Pietrzyk, R. Lanham, S. Gilbert, D. Taylor, J. Amano, R. Bailey, F. Chu, G. Fox, S. Sun, T. Davenport
{"title":"Demonstration of a 4 Mb, high density ferroelectric memory embedded within a 130 nm, 5 LM Cu/FSG logic process","authors":"T. Moise, S. Summerfelt, H. McAdams, S. Aggarwal, K. Udayakumar, F. Celii, J.S. Martin, G. Xing, L. Hall, K. Taylor, T. Hurd, J. Rodriguez, K. Remack, M. D. Khan, K. Boku, G. Stacey, M. Yao, M. Albrecht, E. Zielinski, M. Thakre, S. Kuchimanchi, A. Thomas, B. McKee, J. Rickes, A. Wang, J. Grace, J. Fong, D. Lee, C. Pietrzyk, R. Lanham, S. Gilbert, D. Taylor, J. Amano, R. Bailey, F. Chu, G. Fox, S. Sun, T. Davenport","doi":"10.1109/IEDM.2002.1175897","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175897","url":null,"abstract":"We demonstrate the bit functionality of a low-voltage, embedded ferroelectric random-access memory constructed using a 130 nm gate and five-level Cu/FSG interconnect process. By inserting the two additional masks required for the eFRAM module into this logic flow, we have co-integrated ferroelectric memory and SRAM on a single wafer.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"45 1","pages":"535-538"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77628653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
QDAME simulation of 7.5 nm double-gate Si nFETs with differing access geometries 不同存取几何形状的7.5 nm双栅Si非场效应管的QDAME模拟
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175938
S. Laux, A. Kumar, M. Fischetti
{"title":"QDAME simulation of 7.5 nm double-gate Si nFETs with differing access geometries","authors":"S. Laux, A. Kumar, M. Fischetti","doi":"10.1109/IEDM.2002.1175938","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175938","url":null,"abstract":"We describe QDAME, a new device simulation program which solves self-consistently the Poisson and Schrodinger equations in two space dimensions under the approximation of ballistic transport. The effects of differing access geometries on 7.5 nm double-gate Si FETs are discussed.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"50 1","pages":"715-718"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79127606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Statistics of successive breakdown events for ultra-thin gate oxides 超薄栅极氧化物连续击穿事件的统计
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175800
J. Suñé, E. Wu
{"title":"Statistics of successive breakdown events for ultra-thin gate oxides","authors":"J. Suñé, E. Wu","doi":"10.1109/IEDM.2002.1175800","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175800","url":null,"abstract":"The first oxide breakdown event does not always cause the device or chip failure. In this work, a simple analytical physics-based model is proposed to describe the statistics of successive breakdown events in gate insulators. The results are tested using grouping experiments based on very large sample size statistics. These results are relevant to the reliability of circuit applications where the device (and/or the chip) tolerates several breakdown events without causing device/circuit malfunction. Approximate Weibull distributions valid at the low percentiles relevant to reliability extrapolation are also presented.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"44 1","pages":"147-150"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73418451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
High performance 30 nm bulk CMOS for 65 nm technology node (CMOS5) 面向65纳米技术节点的高性能30纳米体CMOS (CMOS5)
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175924
E. Morifuji, M. Kanda, N. Yanagiya, S. Matsuda, S. Inaba, K. Okano, K. Takahashi, M. Nishigori, H. Tsuno, T. Yamamoto, K. Hiyama, M. Takayanagi, H. Oyamatsu, S. Yamada, T. Noguchi, M. Kakumu
{"title":"High performance 30 nm bulk CMOS for 65 nm technology node (CMOS5)","authors":"E. Morifuji, M. Kanda, N. Yanagiya, S. Matsuda, S. Inaba, K. Okano, K. Takahashi, M. Nishigori, H. Tsuno, T. Yamamoto, K. Hiyama, M. Takayanagi, H. Oyamatsu, S. Yamada, T. Noguchi, M. Kakumu","doi":"10.1109/IEDM.2002.1175924","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175924","url":null,"abstract":"In this paper, we demonstrate high performance CMOS devices developed for the 65 nm technology node. The gate length is shrunk down to 30 nm. The gate oxide is nitrided oxide of 1 nm EOT with an abrupt nitrogen profile. In order to satisfy both the high activation of the gate polysilicon and suppression of the short channel effect, we applied high dose PMOS doping and low temperature spike anneal to the source and drain. Junction leakage is suppressed by applying nickel silicide in such shallow deep junctions. At a supply voltage of 0.85 V, high drive currents (700 /spl mu/A//spl mu/m at Ioff=100 nA//spl mu/m for nMOSFET and 300 /spl mu/A//spl mu/m at Ioff=100 nA//spl mu/m for pMOSFET) and low CV/I values (0.71 ps at Ioff=100 nA//spl mu/m for nMOSFET and 1.41 ps at Ioff=100 nA//spl mu/m for pMOSFET) are achieved. They are the best among published data.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"97 1","pages":"655-658"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75195883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Via design and scaling strategy for nanometer scale interconnect technologies 通过纳米级互连技术的设计和缩放策略
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175909
Sungjun Im, K. Banerjee, K. Goodson
{"title":"Via design and scaling strategy for nanometer scale interconnect technologies","authors":"Sungjun Im, K. Banerjee, K. Goodson","doi":"10.1109/IEDM.2002.1175909","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175909","url":null,"abstract":"Via design and scaling is a critical issue for all nanometer scale interconnect technologies. This paper presents a comprehensive investigation into the robustness and accuracy of ITRS specified design guidelines for vias in nanometer scale technologies. Using rigorous thermal finite element simulations of 3-D via/line structures embedded in a chip, and material/geometrical data based on the ITRS, it is shown that design of vias based on ITRS specified maximum allowable currents for various technology nodes can severely compromise their reliability by underestimating chip-level thermal effects and current flow continuity in pitch matched vias, especially at the local interconnect tier. A more robust via design optimization strategy is proposed which will be useful to process designers.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"2 1","pages":"587-590"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75664040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Suppression of stress-induced voiding in copper interconnects 铜互连中应力诱导空化的抑制
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175948
T. Oshima, K. Hinode, H. Yamaguchi, H. Aoki, K. Torii, T. Saito, K. Ishikawa, J. Noguchi, M. Fukui, T. Nakamura, S. Uno, K. Tsugane, J. Murata, K. Kikushima, H. Sekisaka, E. Murakami, K. Okuyama, T. Iwasaki
{"title":"Suppression of stress-induced voiding in copper interconnects","authors":"T. Oshima, K. Hinode, H. Yamaguchi, H. Aoki, K. Torii, T. Saito, K. Ishikawa, J. Noguchi, M. Fukui, T. Nakamura, S. Uno, K. Tsugane, J. Murata, K. Kikushima, H. Sekisaka, E. Murakami, K. Okuyama, T. Iwasaki","doi":"10.1109/IEDM.2002.1175948","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175948","url":null,"abstract":"Studied stress-induced voiding in Cu interconnects in the temperature range below 250/spl deg/C, and found two different voiding modes. One mode occurs inside a via having wide wire above it, and can be suppressed by optimizing the via shape and the via-cleaning process. The other mode occurs under a via having wide wire below it and can be suppressed by increasing the Cu grain size and improving the adhesion of the barrier metal with Cu.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"56 1","pages":"757-760"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72647229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
Experimental demonstration of a QCA shift register and analysis of errors QCA移位寄存器的实验演示及误差分析
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175787
R. Kummamuru, A. Orlov, R. Ramasubramaniam, C. Lent, G. Bernstein, G. Snider
{"title":"Experimental demonstration of a QCA shift register and analysis of errors","authors":"R. Kummamuru, A. Orlov, R. Ramasubramaniam, C. Lent, G. Bernstein, G. Snider","doi":"10.1109/IEDM.2002.1175787","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175787","url":null,"abstract":"Quantum-dot Cellular Automata (QCA) is a device architecture that uses the position of electrons in quantum-dot arrays to implement digital logic. We present the experimental demonstration of a two-stage QCA shift register and an analysis of errors encountered in its operation.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"241 1","pages":"95-98"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74913421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
High mobility p-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric 高迁移率p沟道锗mosfet与薄氧化氮化锗栅极电介质
Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175873
H. Shang, H. Okorn-Schmidt, K. Chan, M. Copel, J. Ott, P. Kozłowski, S. Steen, S. Cordes, H.-S.P. Wong, E. Jones, W. Haensch
{"title":"High mobility p-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric","authors":"H. Shang, H. Okorn-Schmidt, K. Chan, M. Copel, J. Ott, P. Kozłowski, S. Steen, S. Cordes, H.-S.P. Wong, E. Jones, W. Haensch","doi":"10.1109/IEDM.2002.1175873","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175873","url":null,"abstract":"We report Ge p-channel MOSFETs with a thin gate stack of Ge oxynitride and LTO on bulk Ge substrate without a Si cap layer. Excellent device characteristics (IV and CV) are achieved with subthreshold slope 82mV/dec. /spl sim/40% hole mobility enhancement is obtained over the Si control with a thermal SiO/sub 2/ gate dielectric. To our knowledge, this is the first demonstration of Ge MOSFETs with less than 10nm thick gate dielectric and less than 100mV/dec subthreshold slope.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"129 1","pages":"441-444"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75499397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 127
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