Via design and scaling strategy for nanometer scale interconnect technologies

Sungjun Im, K. Banerjee, K. Goodson
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引用次数: 7

Abstract

Via design and scaling is a critical issue for all nanometer scale interconnect technologies. This paper presents a comprehensive investigation into the robustness and accuracy of ITRS specified design guidelines for vias in nanometer scale technologies. Using rigorous thermal finite element simulations of 3-D via/line structures embedded in a chip, and material/geometrical data based on the ITRS, it is shown that design of vias based on ITRS specified maximum allowable currents for various technology nodes can severely compromise their reliability by underestimating chip-level thermal effects and current flow continuity in pitch matched vias, especially at the local interconnect tier. A more robust via design optimization strategy is proposed which will be useful to process designers.
通过纳米级互连技术的设计和缩放策略
通过设计和缩放是所有纳米级互连技术的关键问题。本文提出了一个全面的调查研究的鲁棒性和准确性的ITRS指定的设计准则的通孔在纳米尺度技术。通过对嵌入芯片的三维通孔/线结构进行严格的热有限元模拟,以及基于ITRS的材料/几何数据,表明基于ITRS规定的各种技术节点的最大允许电流来设计通孔,由于低估了晶片级热效应和节间距匹配通孔中的电流连续性,严重损害了它们的可靠性,特别是在局部互连层。提出了一种鲁棒性更强的工艺设计优化策略。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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CiteScore
4.50
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