T. Moise, S. Summerfelt, H. McAdams, S. Aggarwal, K. Udayakumar, F. Celii, J.S. Martin, G. Xing, L. Hall, K. Taylor, T. Hurd, J. Rodriguez, K. Remack, M. D. Khan, K. Boku, G. Stacey, M. Yao, M. Albrecht, E. Zielinski, M. Thakre, S. Kuchimanchi, A. Thomas, B. McKee, J. Rickes, A. Wang, J. Grace, J. Fong, D. Lee, C. Pietrzyk, R. Lanham, S. Gilbert, D. Taylor, J. Amano, R. Bailey, F. Chu, G. Fox, S. Sun, T. Davenport
{"title":"在130 nm, 5 LM Cu/FSG逻辑过程中嵌入4mb高密度铁电存储器的演示","authors":"T. Moise, S. Summerfelt, H. McAdams, S. Aggarwal, K. Udayakumar, F. Celii, J.S. Martin, G. Xing, L. Hall, K. Taylor, T. Hurd, J. Rodriguez, K. Remack, M. D. Khan, K. Boku, G. Stacey, M. Yao, M. Albrecht, E. Zielinski, M. Thakre, S. Kuchimanchi, A. Thomas, B. McKee, J. Rickes, A. Wang, J. Grace, J. Fong, D. Lee, C. Pietrzyk, R. Lanham, S. Gilbert, D. Taylor, J. Amano, R. Bailey, F. Chu, G. Fox, S. Sun, T. Davenport","doi":"10.1109/IEDM.2002.1175897","DOIUrl":null,"url":null,"abstract":"We demonstrate the bit functionality of a low-voltage, embedded ferroelectric random-access memory constructed using a 130 nm gate and five-level Cu/FSG interconnect process. By inserting the two additional masks required for the eFRAM module into this logic flow, we have co-integrated ferroelectric memory and SRAM on a single wafer.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"45 1","pages":"535-538"},"PeriodicalIF":0.0000,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"45","resultStr":"{\"title\":\"Demonstration of a 4 Mb, high density ferroelectric memory embedded within a 130 nm, 5 LM Cu/FSG logic process\",\"authors\":\"T. Moise, S. Summerfelt, H. McAdams, S. Aggarwal, K. Udayakumar, F. Celii, J.S. Martin, G. Xing, L. Hall, K. Taylor, T. Hurd, J. Rodriguez, K. Remack, M. D. Khan, K. Boku, G. Stacey, M. Yao, M. Albrecht, E. Zielinski, M. Thakre, S. Kuchimanchi, A. Thomas, B. McKee, J. Rickes, A. Wang, J. Grace, J. Fong, D. Lee, C. Pietrzyk, R. Lanham, S. Gilbert, D. Taylor, J. Amano, R. Bailey, F. Chu, G. Fox, S. Sun, T. Davenport\",\"doi\":\"10.1109/IEDM.2002.1175897\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We demonstrate the bit functionality of a low-voltage, embedded ferroelectric random-access memory constructed using a 130 nm gate and five-level Cu/FSG interconnect process. By inserting the two additional masks required for the eFRAM module into this logic flow, we have co-integrated ferroelectric memory and SRAM on a single wafer.\",\"PeriodicalId\":74909,\"journal\":{\"name\":\"Technical digest. International Electron Devices Meeting\",\"volume\":\"45 1\",\"pages\":\"535-538\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-12-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"45\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Technical digest. International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2002.1175897\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Technical digest. International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2002.1175897","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Demonstration of a 4 Mb, high density ferroelectric memory embedded within a 130 nm, 5 LM Cu/FSG logic process
We demonstrate the bit functionality of a low-voltage, embedded ferroelectric random-access memory constructed using a 130 nm gate and five-level Cu/FSG interconnect process. By inserting the two additional masks required for the eFRAM module into this logic flow, we have co-integrated ferroelectric memory and SRAM on a single wafer.
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