H. Shang, H. Okorn-Schmidt, K. Chan, M. Copel, J. Ott, P. Kozłowski, S. Steen, S. Cordes, H.-S.P. Wong, E. Jones, W. Haensch
{"title":"High mobility p-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric","authors":"H. Shang, H. Okorn-Schmidt, K. Chan, M. Copel, J. Ott, P. Kozłowski, S. Steen, S. Cordes, H.-S.P. Wong, E. Jones, W. Haensch","doi":"10.1109/IEDM.2002.1175873","DOIUrl":null,"url":null,"abstract":"We report Ge p-channel MOSFETs with a thin gate stack of Ge oxynitride and LTO on bulk Ge substrate without a Si cap layer. Excellent device characteristics (IV and CV) are achieved with subthreshold slope 82mV/dec. /spl sim/40% hole mobility enhancement is obtained over the Si control with a thermal SiO/sub 2/ gate dielectric. To our knowledge, this is the first demonstration of Ge MOSFETs with less than 10nm thick gate dielectric and less than 100mV/dec subthreshold slope.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"129 1","pages":"441-444"},"PeriodicalIF":0.0000,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"127","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Technical digest. International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2002.1175873","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 127
Abstract
We report Ge p-channel MOSFETs with a thin gate stack of Ge oxynitride and LTO on bulk Ge substrate without a Si cap layer. Excellent device characteristics (IV and CV) are achieved with subthreshold slope 82mV/dec. /spl sim/40% hole mobility enhancement is obtained over the Si control with a thermal SiO/sub 2/ gate dielectric. To our knowledge, this is the first demonstration of Ge MOSFETs with less than 10nm thick gate dielectric and less than 100mV/dec subthreshold slope.