R. Kummamuru, A. Orlov, R. Ramasubramaniam, C. Lent, G. Bernstein, G. Snider
{"title":"Experimental demonstration of a QCA shift register and analysis of errors","authors":"R. Kummamuru, A. Orlov, R. Ramasubramaniam, C. Lent, G. Bernstein, G. Snider","doi":"10.1109/IEDM.2002.1175787","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175787","url":null,"abstract":"Quantum-dot Cellular Automata (QCA) is a device architecture that uses the position of electrons in quantum-dot arrays to implement digital logic. We present the experimental demonstration of a two-stage QCA shift register and an analysis of errors encountered in its operation.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"241 1","pages":"95-98"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74913421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Morifuji, M. Kanda, N. Yanagiya, S. Matsuda, S. Inaba, K. Okano, K. Takahashi, M. Nishigori, H. Tsuno, T. Yamamoto, K. Hiyama, M. Takayanagi, H. Oyamatsu, S. Yamada, T. Noguchi, M. Kakumu
{"title":"High performance 30 nm bulk CMOS for 65 nm technology node (CMOS5)","authors":"E. Morifuji, M. Kanda, N. Yanagiya, S. Matsuda, S. Inaba, K. Okano, K. Takahashi, M. Nishigori, H. Tsuno, T. Yamamoto, K. Hiyama, M. Takayanagi, H. Oyamatsu, S. Yamada, T. Noguchi, M. Kakumu","doi":"10.1109/IEDM.2002.1175924","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175924","url":null,"abstract":"In this paper, we demonstrate high performance CMOS devices developed for the 65 nm technology node. The gate length is shrunk down to 30 nm. The gate oxide is nitrided oxide of 1 nm EOT with an abrupt nitrogen profile. In order to satisfy both the high activation of the gate polysilicon and suppression of the short channel effect, we applied high dose PMOS doping and low temperature spike anneal to the source and drain. Junction leakage is suppressed by applying nickel silicide in such shallow deep junctions. At a supply voltage of 0.85 V, high drive currents (700 /spl mu/A//spl mu/m at Ioff=100 nA//spl mu/m for nMOSFET and 300 /spl mu/A//spl mu/m at Ioff=100 nA//spl mu/m for pMOSFET) and low CV/I values (0.71 ps at Ioff=100 nA//spl mu/m for nMOSFET and 1.41 ps at Ioff=100 nA//spl mu/m for pMOSFET) are achieved. They are the best among published data.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"97 1","pages":"655-658"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75195883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Oshima, K. Hinode, H. Yamaguchi, H. Aoki, K. Torii, T. Saito, K. Ishikawa, J. Noguchi, M. Fukui, T. Nakamura, S. Uno, K. Tsugane, J. Murata, K. Kikushima, H. Sekisaka, E. Murakami, K. Okuyama, T. Iwasaki
{"title":"Suppression of stress-induced voiding in copper interconnects","authors":"T. Oshima, K. Hinode, H. Yamaguchi, H. Aoki, K. Torii, T. Saito, K. Ishikawa, J. Noguchi, M. Fukui, T. Nakamura, S. Uno, K. Tsugane, J. Murata, K. Kikushima, H. Sekisaka, E. Murakami, K. Okuyama, T. Iwasaki","doi":"10.1109/IEDM.2002.1175948","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175948","url":null,"abstract":"Studied stress-induced voiding in Cu interconnects in the temperature range below 250/spl deg/C, and found two different voiding modes. One mode occurs inside a via having wide wire above it, and can be suppressed by optimizing the via shape and the via-cleaning process. The other mode occurs under a via having wide wire below it and can be suppressed by increasing the Cu grain size and improving the adhesion of the barrier metal with Cu.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"56 1","pages":"757-760"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72647229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Moise, S. Summerfelt, H. McAdams, S. Aggarwal, K. Udayakumar, F. Celii, J.S. Martin, G. Xing, L. Hall, K. Taylor, T. Hurd, J. Rodriguez, K. Remack, M. D. Khan, K. Boku, G. Stacey, M. Yao, M. Albrecht, E. Zielinski, M. Thakre, S. Kuchimanchi, A. Thomas, B. McKee, J. Rickes, A. Wang, J. Grace, J. Fong, D. Lee, C. Pietrzyk, R. Lanham, S. Gilbert, D. Taylor, J. Amano, R. Bailey, F. Chu, G. Fox, S. Sun, T. Davenport
{"title":"Demonstration of a 4 Mb, high density ferroelectric memory embedded within a 130 nm, 5 LM Cu/FSG logic process","authors":"T. Moise, S. Summerfelt, H. McAdams, S. Aggarwal, K. Udayakumar, F. Celii, J.S. Martin, G. Xing, L. Hall, K. Taylor, T. Hurd, J. Rodriguez, K. Remack, M. D. Khan, K. Boku, G. Stacey, M. Yao, M. Albrecht, E. Zielinski, M. Thakre, S. Kuchimanchi, A. Thomas, B. McKee, J. Rickes, A. Wang, J. Grace, J. Fong, D. Lee, C. Pietrzyk, R. Lanham, S. Gilbert, D. Taylor, J. Amano, R. Bailey, F. Chu, G. Fox, S. Sun, T. Davenport","doi":"10.1109/IEDM.2002.1175897","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175897","url":null,"abstract":"We demonstrate the bit functionality of a low-voltage, embedded ferroelectric random-access memory constructed using a 130 nm gate and five-level Cu/FSG interconnect process. By inserting the two additional masks required for the eFRAM module into this logic flow, we have co-integrated ferroelectric memory and SRAM on a single wafer.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"45 1","pages":"535-538"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77628653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Nitride-sandwiched-oxide gate insulator for low power CMOS","authors":"D. Ishikawa, S. Sakai, K. Katsuyama, A. Hiraiwa","doi":"10.1109/IEDM.2002.1175975","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175975","url":null,"abstract":"A gate insulator with a novel nitride-sandwiched oxide (NSO) structure was formed by successive NO and plasma nitridation steps. This approach reduced the leakage current to 15% of the oxide value, while enhancing the electron mobility by 15%. NSO also has high dielectric reliability and almost completely blocks B penetration in a PMOS device. Our experiments have confirmed that NSO is a very promising technology for forming gate insulators in low-power CMOS devices in the 100-nm to 80-nm node.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"92 1","pages":"869-872"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76389191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Samavedam, L. La, J. Smith, S. Dakshina-Murthy, E. Luckowski, J. Schaeffer, M. Zavala, R. Martin, V. Dhandapani, D. Triyoso, H. Tseng, P. Tobin, D. Gilmer, C. Hobbs, W. Taylor, J. Grant, R. Hegde, J. Mogab, C. Thomas, P. Abramowitz, M. Moosa, J. Conner, J. Jiang, V. Arunachalarn, M. Sadd, B. Nguyen, B. White
{"title":"Dual-metal gate CMOS with HfO2 gate dielectric","authors":"S. Samavedam, L. La, J. Smith, S. Dakshina-Murthy, E. Luckowski, J. Schaeffer, M. Zavala, R. Martin, V. Dhandapani, D. Triyoso, H. Tseng, P. Tobin, D. Gilmer, C. Hobbs, W. Taylor, J. Grant, R. Hegde, J. Mogab, C. Thomas, P. Abramowitz, M. Moosa, J. Conner, J. Jiang, V. Arunachalarn, M. Sadd, B. Nguyen, B. White","doi":"10.1109/IEDM.2002.1175871","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175871","url":null,"abstract":"We report for the first time on a novel dual-metal gate CMOS integration on HfO/sub 2/ gate dielectric using TiN (PMOS) and TaSiN (NMOS) gate electrodes. Compared to a single metal integration, the dual-metal integration does not degrade gate leakage, mobility and charge trapping behavior. Promising preliminary TDDB data were obtained from dual-metal gate MOSFETs, while still delivering much improved gate leakage (10/sup 4/ - 10/sup 5/ X better than SiO/sub 2/).","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"28 1","pages":"433-436"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76749912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Via design and scaling strategy for nanometer scale interconnect technologies","authors":"Sungjun Im, K. Banerjee, K. Goodson","doi":"10.1109/IEDM.2002.1175909","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175909","url":null,"abstract":"Via design and scaling is a critical issue for all nanometer scale interconnect technologies. This paper presents a comprehensive investigation into the robustness and accuracy of ITRS specified design guidelines for vias in nanometer scale technologies. Using rigorous thermal finite element simulations of 3-D via/line structures embedded in a chip, and material/geometrical data based on the ITRS, it is shown that design of vias based on ITRS specified maximum allowable currents for various technology nodes can severely compromise their reliability by underestimating chip-level thermal effects and current flow continuity in pitch matched vias, especially at the local interconnect tier. A more robust via design optimization strategy is proposed which will be useful to process designers.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"2 1","pages":"587-590"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75664040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Verzellesi, R. Pierobon, F. Rampazzo, G. Meneghesso, A. Chini, U. Mishra, C. Canali, E. Zanoni
{"title":"Experimental/numerical investigation on current collapse in AlGaN/GaN HEMT's","authors":"G. Verzellesi, R. Pierobon, F. Rampazzo, G. Meneghesso, A. Chini, U. Mishra, C. Canali, E. Zanoni","doi":"10.1109/IEDM.2002.1175932","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175932","url":null,"abstract":"Rf current collapse is investigated in AlGaN/GaN HEMT's by means of pulsed, transient, and small-signal measurements. Numerical device simulations are presented, showing that the concomitant presence, at the ungated device surface, of polarization-induced charges and hole traps can explain, without invoking any other hypothesis, all dispersion effects observed experimentally.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"44 1","pages":"689-692"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81344653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Rieh, B. Jagannathan, H. Chen, K. Schonenberg, D. Angell, A. Chinthakindi, J. Florkey, F. Golan, D. Greenberg, S. Jeng, M. Khater, F. Pagette, C. Schnabel, Peter Andrew Smith, A. Stricker, K. Vaed, R. Volant, D. Ahlgren, G. Freeman, K. Stein, S. Subbanna
{"title":"SiGe HBTs with cut-off frequency of 350 GHz","authors":"J. Rieh, B. Jagannathan, H. Chen, K. Schonenberg, D. Angell, A. Chinthakindi, J. Florkey, F. Golan, D. Greenberg, S. Jeng, M. Khater, F. Pagette, C. Schnabel, Peter Andrew Smith, A. Stricker, K. Vaed, R. Volant, D. Ahlgren, G. Freeman, K. Stein, S. Subbanna","doi":"10.1109/IEDM.2002.1175952","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175952","url":null,"abstract":"This work reports on SiGe HBTs with f/sub T/ of 350 GHz. This is the highest reported f/sub T/ for any Si-based transistor as well as any bipolar transistor. Associated f/sub max/ is 170 GHz, and BV/sub CEO/ and BV/sub CBO/ are measured to be 1.4 V and 5.0 V, respectively. Also achieved was the simultaneous optimization of f/sub T/ and f/sub max/ resulting in 270 GHz and 260 GHz, with BV/sub CEO/ and BV/sub CBO/ of 1.6 V and 5.5 V, respectively. The dependence of device performance on bias condition and device dimension has been investigated. Considerations regarding the extraction of such high f/sub T/ and f/sub max/ values are also discussed.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"25 1","pages":"771-774"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81933605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Oh, H. Kang, H. Ryu, M. Oh, H.S. Jung, Y.S. Kim, J. He, N. Lee, K. Cho, D. Lee, T. Yang, I. Cho, H. Kang, Y.W. Kim, K. Suh
{"title":"Manufacturable embedded CMOS 6T-SRAM technology with high-k gate dielectric device for system-on-chip applications","authors":"C. Oh, H. Kang, H. Ryu, M. Oh, H.S. Jung, Y.S. Kim, J. He, N. Lee, K. Cho, D. Lee, T. Yang, I. Cho, H. Kang, Y.W. Kim, K. Suh","doi":"10.1109/IEDM.2002.1175869","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175869","url":null,"abstract":"Manufacturable embedded CMOS 6T-SRAM with the HfO/sub 2/-Al/sub 2/O/sub 3/ dielectric for system-on-chip (SoC) applications is successfully demonstrated for the first time in the semiconductor industry. The possibility of the high-k gate dielectric in low power SoC applications is suggested. 0.11/spl mu/m NFET and PFET devices with thin high-k gate dielectric have 470 and 150/spl mu/A//spl mu/m at Ioff=0.1nA/um and Vdd=1.2V, respectively. Inversion thickness of NFET and PFET are 2.4nm and 2.7nm, respectively. Gate leakage current of the high-k is 1000 times lower than that of the oxynitride at the accumulation region. Static noise margin of 2.14/spl mu/m/sup 2/ 6T-SRAM bit cell is about 300mV at Vdd=1.2V. 6T-SRAM chip yield of the high-k is comparable to that of the oxynitride. The post nitridation after high-k film deposition is very important to the yield of the SRAM chips due to the suppression of the PFET boron penetration. Stand-by current of the SRAM chips with the high-k is shown to be a decreases of 60% compared with the oxynitride.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"17 1","pages":"423-426"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86936183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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