Technical digest. International Electron Devices Meeting最新文献_第5页

Experimental/numerical investigation on current collapse in AlGaN/GaN HEMT's AlGaN/GaN HEMT电流崩塌的实验/数值研究

Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175932

G. Verzellesi, R. Pierobon, F. Rampazzo, G. Meneghesso, A. Chini, U. Mishra, C. Canali, E. Zanoni

引用次数: 22

Improved current performance of CMOSFETs with nitrogen incorporated HfO2-Al2O3 laminate gate dielectric 氮掺杂HfO2-Al2O3层压栅电介质改善了cmosfet的电流性能

Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175971

Hyung-Seok Jung, Yun-seok Kim, Jong Pyo Kim, Jung Hyoung Lee, Jong-Ho Lee, N. Lee, Ho-Kyu Kang, K. Suh, H. Ryu, C. Oh, Young-Wug Kim, K. Cho, H. Baik, Youngsu Chung, H. Chang, D. Moon

{"title":"Improved current performance of CMOSFETs with nitrogen incorporated HfO2-Al2O3 laminate gate dielectric","authors":"Hyung-Seok Jung, Yun-seok Kim, Jong Pyo Kim, Jung Hyoung Lee, Jong-Ho Lee, N. Lee, Ho-Kyu Kang, K. Suh, H. Ryu, C. Oh, Young-Wug Kim, K. Cho, H. Baik, Youngsu Chung, H. Chang, D. Moon","doi":"10.1109/IEDM.2002.1175971","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175971","url":null,"abstract":"For the first time, we integrated poly-Si gate CMOSFETs with nitrogen incorporated HfO/sub 2/-Al/sub 2/O/sub 3/ laminate (HfAlON) as gate dielectrics. Both low gate leakage currents (0.1 mA/cm/sup 2/ at V/sub g/=+1.0 V) and low EOT (15.6 /spl Aring/) sufficiently satisfy the specifications (EOT=12/spl sim/20 /spl Aring/, J/sub g/=2.2 mA/cm/sup 2/) estimated by ITRS for low power applications. By in-situ 3 step post-deposition annealing, approximately 17 at.% nitrogen is incorporated at the HfAlON/Si interface. In-situ 3 step post-deposition annealing decreases metallic Hf bonding, which exists at the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate/Si interface. As a result, we can suppress C-V hysteresis and improve current performance. Finally, well-behaved 100 nm CMOSFET devices are achieved. The measured saturation currents at 1.2 V V/sub dd/ are 585 /spl mu//spl Aring///spl mu/m (I/sub off/= 10 nA//spl mu/m) for nMOSFET and 265 /spl mu/A//spl mu/m (I/sub off/=10 nA//spl mu/m) for pMOSFET, which are approximately 80% of those of nitrided SiO/sub 2/. In terms of I/sub on/-I/sub off/ characteristics of n/pMOSFETs, these results represent the best current performance compared with previous reports for poly-Si gate CMOSFETs with high-k gate dielectrics.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"56 1","pages":"853-856"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90592305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Manufacturable embedded CMOS 6T-SRAM technology with high-k gate dielectric device for system-on-chip applications 可制造嵌入式CMOS 6T-SRAM技术，具有高k栅极介电器件，用于片上系统应用

Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175869

C. Oh, H. Kang, H. Ryu, M. Oh, H.S. Jung, Y.S. Kim, J. He, N. Lee, K. Cho, D. Lee, T. Yang, I. Cho, H. Kang, Y.W. Kim, K. Suh

{"title":"Manufacturable embedded CMOS 6T-SRAM technology with high-k gate dielectric device for system-on-chip applications","authors":"C. Oh, H. Kang, H. Ryu, M. Oh, H.S. Jung, Y.S. Kim, J. He, N. Lee, K. Cho, D. Lee, T. Yang, I. Cho, H. Kang, Y.W. Kim, K. Suh","doi":"10.1109/IEDM.2002.1175869","DOIUrl":"https://doi.org/10.1109/IEDM.2002.1175869","url":null,"abstract":"Manufacturable embedded CMOS 6T-SRAM with the HfO/sub 2/-Al/sub 2/O/sub 3/ dielectric for system-on-chip (SoC) applications is successfully demonstrated for the first time in the semiconductor industry. The possibility of the high-k gate dielectric in low power SoC applications is suggested. 0.11/spl mu/m NFET and PFET devices with thin high-k gate dielectric have 470 and 150/spl mu/A//spl mu/m at Ioff=0.1nA/um and Vdd=1.2V, respectively. Inversion thickness of NFET and PFET are 2.4nm and 2.7nm, respectively. Gate leakage current of the high-k is 1000 times lower than that of the oxynitride at the accumulation region. Static noise margin of 2.14/spl mu/m/sup 2/ 6T-SRAM bit cell is about 300mV at Vdd=1.2V. 6T-SRAM chip yield of the high-k is comparable to that of the oxynitride. The post nitridation after high-k film deposition is very important to the yield of the SRAM chips due to the suppression of the PFET boron penetration. Stand-by current of the SRAM chips with the high-k is shown to be a decreases of 60% compared with the oxynitride.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"17 1","pages":"423-426"},"PeriodicalIF":0.0,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86936183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Device performance of sub-50 nm CMOS with ultra-thin plasma nitrided gate dielectrics 采用超薄等离子体氮化栅极电介质的50 nm以下CMOS器件性能

Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175923

S. Inaba, T. Shimizu, S. Mori, K. Sekine, K. Saki, H. Suto, H. Fukui, M. Nagamine, M. Fujiwara, T. Yamamoto, M. Takayanagi, I. Mizushima, K. Okano, S. Matsuda, H. Oyamatsu, Y. Tsunashima, S. Yamada, Y. Toyoshima, H. Ishiuchi

引用次数: 11

A new model of time evolution of gate leakage current after soft breakdown in ultra-thin gate oxides 超薄栅极氧化物软击穿后栅漏电流时间演化的新模型

Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175802

T. Hosoi, P. L. Lo Re, Y. Kamakura, K. Taniguchi

引用次数: 42

Does source-to-drain tunneling limit the ultimate scaling of MOSFETs? 源极-漏极隧道是否限制了mosfet的最终缩放?

Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175936

Jing Wang, M. Lundstrom

引用次数: 147

Transistors with dual work function metal gates by single full silicidation (FUSI) of polysilicon gates 采用多晶硅栅极的单次全硅化(FUSI)方法制备具有双功功能金属栅极的晶体管

Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175854

W. Maszara, Z. Krivokapic, P. King, J. Goo, M. Lin

引用次数: 72

Transistor delay analysis and effective channel velocity extraction in AlGaN/GaN HFETs AlGaN/GaN hfet晶体管延迟分析及有效通道速度提取

Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175931

C. Bolognesi, A.C. Kwan, D. Disanto

引用次数: 11

Strained silicon MOSFET technology 应变硅MOSFET技术

Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175770

J. Hoyt, H. Nayfeh, S. Eguchi, I. Åberg, Guangrui Xia, T. Drake, Eugene A. Fitzgerald, D. Antoniadis

引用次数: 242

SiGe HBTs with cut-off frequency of 350 GHz 截止频率为350 GHz的SiGe hbt

Technical digest. International Electron Devices Meeting Pub Date : 2002-12-08 DOI: 10.1109/IEDM.2002.1175952

J. Rieh, B. Jagannathan, H. Chen, K. Schonenberg, D. Angell, A. Chinthakindi, J. Florkey, F. Golan, D. Greenberg, S. Jeng, M. Khater, F. Pagette, C. Schnabel, Peter Andrew Smith, A. Stricker, K. Vaed, R. Volant, D. Ahlgren, G. Freeman, K. Stein, S. Subbanna

引用次数: 194