W. Maszara, Z. Krivokapic, P. King, J. Goo, M. Lin
{"title":"采用多晶硅栅极的单次全硅化(FUSI)方法制备具有双功功能金属栅极的晶体管","authors":"W. Maszara, Z. Krivokapic, P. King, J. Goo, M. Lin","doi":"10.1109/IEDM.2002.1175854","DOIUrl":null,"url":null,"abstract":"Metal gate electrodes with two different work functions, /spl sim/4.5 and /spl sim/4.9 eV for NMOS and PMOS, respectively, were obtained by single-step full silicidation of poly gates. Reduction of polysilicon depletion was /spl sim/0.25 nm. Pile-up of arsenic at the NMOS dielectric is believed responsible for NiSi work function modification. Metal gate may offer little or no gate current reduction for the same T/sub oxinv/ as poly gate.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"32 1 1","pages":"367-370"},"PeriodicalIF":0.0000,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"72","resultStr":"{\"title\":\"Transistors with dual work function metal gates by single full silicidation (FUSI) of polysilicon gates\",\"authors\":\"W. Maszara, Z. Krivokapic, P. King, J. Goo, M. Lin\",\"doi\":\"10.1109/IEDM.2002.1175854\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Metal gate electrodes with two different work functions, /spl sim/4.5 and /spl sim/4.9 eV for NMOS and PMOS, respectively, were obtained by single-step full silicidation of poly gates. Reduction of polysilicon depletion was /spl sim/0.25 nm. Pile-up of arsenic at the NMOS dielectric is believed responsible for NiSi work function modification. Metal gate may offer little or no gate current reduction for the same T/sub oxinv/ as poly gate.\",\"PeriodicalId\":74909,\"journal\":{\"name\":\"Technical digest. International Electron Devices Meeting\",\"volume\":\"32 1 1\",\"pages\":\"367-370\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-12-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"72\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Technical digest. International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2002.1175854\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Technical digest. International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2002.1175854","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Transistors with dual work function metal gates by single full silicidation (FUSI) of polysilicon gates
Metal gate electrodes with two different work functions, /spl sim/4.5 and /spl sim/4.9 eV for NMOS and PMOS, respectively, were obtained by single-step full silicidation of poly gates. Reduction of polysilicon depletion was /spl sim/0.25 nm. Pile-up of arsenic at the NMOS dielectric is believed responsible for NiSi work function modification. Metal gate may offer little or no gate current reduction for the same T/sub oxinv/ as poly gate.