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Review of thin film porosity characterization approaches 薄膜孔隙度表征方法综述
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919811
K. Mogilnikov, Dongchen Che, M. Baklanov, Kangning Xu, Kaidong Xu
{"title":"Review of thin film porosity characterization approaches","authors":"K. Mogilnikov, Dongchen Che, M. Baklanov, Kangning Xu, Kaidong Xu","doi":"10.1109/CSTIC.2017.7919811","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919811","url":null,"abstract":"The most important properties of porous thin films depend on the pore structure. The evaluation of porosity is of great importance for analyzing their pore structure. Some known methods were adapted and proposed for the study of thin films porosity, such as microscope techniques, radiation scattering, wave propagation, gas adsorption. Besides, there are some new approaches developed for thin film porosity, such as X-ray porosimetry, positron annihilation lifetime spectroscopy, quartz crystal microbalance, and ellipsometric porosimetry. In this paper, the possibilities of various methods of studying thin films porosity will be discussed, including the latest developments in this area.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"73 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88509884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Study of safe operating area and improvement for power management integrated circuit 电源管理集成电路安全工作区域的研究与改进
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919833
Sarah Zhou, Y. Song, Kary Chien, Canny Chen
{"title":"Study of safe operating area and improvement for power management integrated circuit","authors":"Sarah Zhou, Y. Song, Kary Chien, Canny Chen","doi":"10.1109/CSTIC.2017.7919833","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919833","url":null,"abstract":"LDMOS (Lateral Double-diffused Metal Oxide Semiconductor) is widely used to smart power management IC, which can be attributed to its high operation voltage and high current driving capability. Furthermore, LDMOS is compatible with conventional CMOS processes. It will be much easier for IC foundries to make it by existing process flows. Operating at both a high drain voltage and a high current, LDMOS is more sensitive to hot carrier degradation than the devices with low operation voltages [1]. Thus, the LDMOS HC-SOA (Hot Carrier Safe Operating Area) is a major reliability concern and requires more attentions. In this paper, the HC-SOA's of conventional core and IO MOS are also illustrated to show different failure mechanisms and we focus on the detailed HC-SOA test method in practice. Additionally, we study the SOA contours for different cores, IO, NPMOS and LDMOS. Finally, we discuss the HC-SOA extension methods for LDMOS.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"6 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87031314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Investigation of multiple soft breakdown during time-dependent dielectric breakdown 时变介质击穿过程中多次软击穿的研究
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919839
Qiwei Wu, Bin. F. Yin, Ke Zhou, Jiong Wang, Jinde Gao
{"title":"Investigation of multiple soft breakdown during time-dependent dielectric breakdown","authors":"Qiwei Wu, Bin. F. Yin, Ke Zhou, Jiong Wang, Jinde Gao","doi":"10.1109/CSTIC.2017.7919839","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919839","url":null,"abstract":"In this paper, we studied the multiple soft breakdown phenomena of gate oxide during TDDB (Time Dependent Dielectric Breakdown). After the soft breakdown, the parameters of the device had been greatly degraded (as a result, the device lost its original functions), although the multiple soft breakdown did not lead the oxide catastrophical failure. Further analysis also verified that the gate oxide had been damaged after the first soft breakdown. We found that there is a very good match between the times of soft breakdown and the failure points fixed using EMMI-OBIRCH system. Moreover, such correspondence was verified using the in-situ failure analysis method. Finally, we proposed an explanation concerning the oxide breakdown based on the phenomenon.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"47 3 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77320950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Monolithic 3D (M3D) reconfigurable logic applications using extremely-low-power electron devices 使用极低功耗电子器件的单片3D (M3D)可重构逻辑应用
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919753
W. Choi
{"title":"Monolithic 3D (M3D) reconfigurable logic applications using extremely-low-power electron devices","authors":"W. Choi","doi":"10.1109/CSTIC.2017.7919753","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919753","url":null,"abstract":"CMOS and nano-electromechanical (NEM) hybrid reconfigurable logic (RL) circuits are implemented by using monolithic three-dimensional (M3D) integration process. Their operation and feasibility are discussed based on simulation and experimental results.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"28 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83798038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The solutions for 3D-NAND processes with Canon's latest KrF scanner 3D-NAND工艺的解决方案与佳能最新的KrF扫描仪
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919772
M. Yamada, Hajime Takeuchi, K. Mishima, K. Yoshimura, Kazuhiro Takahashi
{"title":"The solutions for 3D-NAND processes with Canon's latest KrF scanner","authors":"M. Yamada, Hajime Takeuchi, K. Mishima, K. Yoshimura, Kazuhiro Takahashi","doi":"10.1109/CSTIC.2017.7919772","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919772","url":null,"abstract":"The NAND type flash-memory is now used not only on smart phones or tablet PCs, but also adopted on infrastructures such as servers, etc.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"6 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83148804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Systematic maintenance and applications of Failure Modes and Effects Analysis (FMEA) in semiconductor manufacturing 失效模式和影响分析(FMEA)在半导体制造中的系统维护和应用
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919853
Hongtao H. T. Qian, Z. Liu, Yuhong Betsy Xu
{"title":"Systematic maintenance and applications of Failure Modes and Effects Analysis (FMEA) in semiconductor manufacturing","authors":"Hongtao H. T. Qian, Z. Liu, Yuhong Betsy Xu","doi":"10.1109/CSTIC.2017.7919853","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919853","url":null,"abstract":"Failure Modes and Effects Analysis (FMEA) is considered as a systematic, learning retention vehicle in semiconductor manufacturing. This paper tries to set up a quantized evaluation approach on FMEA effectiveness for the first time and also presents a systematic maintenance method of FMEA in Foundry (FAB) to instead of traditional paper works which realizes intelligent maintenance to increase the timeliness and accuracy of FMEA. And, cross system applications between e-FMEA system and other FAB manufacture and monitor systems are presented to show the effectiveness improve after systematization.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"19 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83351993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Highly effective low-k dielectric test structures and reliability assessment for 28NM technology node and beyond 28NM及以上技术节点高效低k介电测试结构及可靠性评估
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919829
Zhijuan Wang, Yueqin Zhu, Kai Wang, Yuzhu Gao, W. Chien
{"title":"Highly effective low-k dielectric test structures and reliability assessment for 28NM technology node and beyond","authors":"Zhijuan Wang, Yueqin Zhu, Kai Wang, Yuzhu Gao, W. Chien","doi":"10.1109/CSTIC.2017.7919829","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919829","url":null,"abstract":"Low-k/ultra-low-k dielectric is expected to have large-scale implementation in the manufacturing of modern advanced IC technology nodes. The reliability performance of a low-k dielectric must meet the given target lifetime based on semiconductor electrical requirements. Reliability test structures are specifically devised in this paper. We proposed a series of fundamental improvements on test structures in terms of practical applications. Our data shows that intrinsic reliability of the low-k dielectrics can be further optimized through the process tuning without the variation in k value.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"9 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86902718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Thin-film processing of “exotic” phase-change and ferroelectric materials for IoT applications 用于物联网应用的“外来”相变和铁电材料的薄膜加工
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919878
K. Suu, I. Kimura, H. Kobayashi, Y. Miyaguchi, T. Masuda, Y. Kokaze, T. Jimbo
{"title":"Thin-film processing of “exotic” phase-change and ferroelectric materials for IoT applications","authors":"K. Suu, I. Kimura, H. Kobayashi, Y. Miyaguchi, T. Masuda, Y. Kokaze, T. Jimbo","doi":"10.1109/CSTIC.2017.7919878","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919878","url":null,"abstract":"We will report our development results of phase-change and ferroelectric thin film processing technologies including sputtering, MOCVD and plasma etching as well as manufacturing processes for PCRAM, FRAM and MEMS/Sensor device applications. Thin-film functional material such as phase-change materials and ferroelectric materials have been utilized to form advanced semiconductor and electronic devices for internet of things (IoT) solutions. We are confident our manufacturing technologies for these materials and devices will contribute to realizing next generation Smart Society.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"100 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88541664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A concise and precise model of the gate delay for EDA simulation 一个简洁精确的栅极延迟EDA仿真模型
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919892
Zhipeng Yue, Zhuoquan Huang, Dihu Chen, Tao Su
{"title":"A concise and precise model of the gate delay for EDA simulation","authors":"Zhipeng Yue, Zhuoquan Huang, Dihu Chen, Tao Su","doi":"10.1109/CSTIC.2017.7919892","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919892","url":null,"abstract":"This paper considers the relationship between the static gate delay and the supply voltage of the digital integrated circuit. An empirical equation with physical implication is proposed for calculating the static gate delay. The expression of the gate delay is very simple. It contains only three constants. The calculation includes only one subtraction step, one division step and one addition step. Transistor level simulations are performed to verify the equation. The model matches the experiment results precisely. It is valid for various technologies, gate types, and operation temperatures. The equation can be applied in EDA tools to simulate the timing of the circuit under the PVT variation and the electromagnetic interference.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"1 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88897875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Analytical modeling for substrate effect of lateral power devices 横向功率器件衬底效应的解析建模
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919734
J. Chen, Yufeng Guo, Man Li, Ling Du, Xinchun Ji, Changchun Zhang, Jiafei Yao
{"title":"Analytical modeling for substrate effect of lateral power devices","authors":"J. Chen, Yufeng Guo, Man Li, Ling Du, Xinchun Ji, Changchun Zhang, Jiafei Yao","doi":"10.1109/CSTIC.2017.7919734","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919734","url":null,"abstract":"A two-dimensional(2-D) analytical model for substrate effect of lateral power devices is developed. By solving the 2-D Poisson's equation, an analytical model is proposed and verified by the agreements between the analytical results and numerical simulation results using MEDICI. It suggests that the optimized substrate voltage modules the distributions of the surface potential and electrical field, whose effect is equivalent to changing the concentration of the drift region. As a result, the breakdown voltage is improved.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"40 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76182245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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